Pixel Circuit Preliminary Charging for OLED Display Quality

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Solution Overview

Problem

In organic EL display devices, the short selection period for scanning lines at higher resolutions and frequencies leads to insufficient charging of the gate node voltage, resulting in decreased display quality, especially when using transistors with low mobility such as amorphous silicon, microcrystalline silicon, or IGZO-TFTs.

Innovation Solution

A pixel circuit design that includes a drive transistor, a drive capacitance element, and multiple input transistors connected to preceding scanning lines to perform preliminary charging, ensuring the drive capacitance element is charged to a desired voltage even with low mobility transistors or insufficient selection periods, maintaining display quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If transistors with low mobility (amorphous silicon, microcrystalline silicon, IGZO-TFTs) are used in pixel circuits, then device complexity is reduced and ease of manufacture is improved, but the charging time increases and display quality deteriorates due to insufficient charging of the gate node voltage within the selection period

Engineering Contradiction:
Improveease of manufactureVSAvoiddisplay quality
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by introducing a preliminary charging period before the main selection period. During this preliminary period, the gate node voltage is pre-charged to reduce the charging burden during the subsequent main selection period. This allows low mobility transistors to achieve sufficient gate node voltage charging without requiring excessively long selection periods, thereby maintaining display quality while using easier-to-manufacture low mobility transistor materials.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the selection period for scanning lines is shortened to increase driving frequency and resolution, then productivity is improved, but the gate node voltage charging becomes insufficient and display quality deteriorates

Engineering Contradiction:
ImproveproductivityVSAvoiddisplay quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the selection period into two distinct parts: a preliminary charging period and a main selection period. The preliminary charging period is dedicated solely to charging the gate node voltage, while the main selection period handles data writing and other operations. This segmentation allows the gate node voltage to be adequately charged even when the total selection period is shortened for high-resolution, high-frequency driving, thereby maintaining display quality while improving productivity.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If the selection period is extended to ensure sufficient charging of the gate node voltage, then display quality is improved, but the driving frequency must be reduced and productivity deteriorates

Engineering Contradiction:
Improvedisplay qualityVSAvoidproductivity
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

By performing the gate node voltage charging in advance during the preliminary charging period, the patent eliminates the need to extend the main selection period for charging purposes. This allows the main selection period to be kept short for high-frequency driving while still achieving sufficient gate node voltage charging through the preliminary action, thereby maintaining both display quality and productivity.

Inventive Principle:
Principle #10Preliminary action

4Device complexity

If a single input transistor is used in the pixel circuit, then device complexity is reduced, but the charging time becomes insufficient for low mobility transistors and display quality deteriorates

Engineering Contradiction:
Improvedevice complexityVSAvoiddisplay quality
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent introduces a preliminary charging period as a temporal extension rather than adding more physical transistors. This preliminary action allows the single input transistor to perform its charging function more effectively by dedicating a specific time period solely to gate node voltage charging, thereby maintaining device simplicity while improving charging sufficiency and display quality.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The preliminary charging mechanism effectively reduces the charging time and ensures the drive capacitance element is charged to the desired voltage, maintaining display quality even with transistors of low mobility or short selection periods, enhancing reliability across various resolutions and frequencies.

Implementation Method 1

a drive capacitance element which holds a voltage for controlling the drive transistor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9633599B2Pixel circuit, display device including the same and driving method of the display device
Publication Date: 2017.04.25 SHARP KK
  • US9633599B2 patent drawing
  • US9633599B2 patent drawing
  • US9633599B2 patent drawing

AI summary

A pixel circuit is capable of maintaining a display quality even in cases where an input transistor has a low mobility, or where it is impossible to take a sufficient selection period for each scanning line. A pixel circuit includes an organic EL element (OLED), transistors, and a capacitor. A drive transistor has its drain terminal connected to a HIGH level power supply line, and has its source terminal connected to an anode terminal of the OLED. The first input transistor has its gate terminal connected to a scanning line Si, and is disposed between a data line Dj and the gate terminal of the drive transistor. The second input transistor has its gate terminal connected to a scanning line (Si−1) in the (i−1)th row, and is disposed between a data line and the gate terminal of the drive transistor. The capacitor is disposed between the gate terminal and the source terminal of the drive transistor.