Pixel Circuit Pull-Low Switch for RC Delay Reduction
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Solution Overview
Problem
In liquid crystal display panels, the resistive capacitive delay (RC delay) results in long falling times for gate driving signals, leading to insufficient charging time, which worsens in high-resolution displays and reduces image quality.
Innovation Solution
The implementation of a pull-low switch in the pixel circuit that quickly pulls the gate signal to a reference low voltage after the driving time period finishes, reducing the time required for the gate signal to fall and eliminating the need for pre-disabling, thereby ensuring sufficient charging time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If gate driving signals are used to drive pixel circuits in liquid crystal display panels, then the display panel can operate and display images, but the resistive capacitive delay (RC delay) causes long falling times for gate driving signals, resulting in insufficient charging time for pixel capacitors
Solution Approach 1:
The gate driving signal control is segmented into two independent parts: the original gate signal for turning on the pixel circuit, and a separate pull-low signal for rapidly discharging the gate line. This segmentation allows the gate signal to remain high during the entire charging period without being constrained by RC delay, while the pull-low signal independently controls the rapid falling edge when needed.
Solution Approach 2:
A pull-low switch is introduced as an intermediary component between the gate line and ground. This switch acts as a mediator that can rapidly discharge the gate line capacitance when activated by the pull-low signal, effectively overcoming the RC delay limitation and enabling precise control of the gate signal falling edge independent of the natural RC discharge time constant.
2Duration of action of moving object
If the gate signal falling time is reduced to increase charging time, then pixel capacitor charging becomes sufficient, but the gate signal cannot be disabled quickly enough for subsequent pixel operations
Solution Approach 1:
The pull-low switch is prepared in advance and remains in the off state during the gate signal high period. When the pull-low signal is applied, the switch is already positioned to immediately discharge the gate line, enabling rapid gate signal disabling without affecting the previous charging phase. This preliminary positioning allows the system to switch between charging and disabling modes instantly.
Solution Approach 2:
The gate line discharge mechanism is made dynamic through the pull-low switch, which can transition between high-impedance (off) and low-impedance (on) states. During the charging phase, the switch is off, allowing the gate signal to remain stable. When disabling is needed, the switch transitions to on state, creating a rapid discharge path that dynamically overrides the RC time constant.
3Manufacturing precision
If a pull-low switch is added to rapidly discharge the gate signal, then charging time is increased and display quality improves, but the pixel circuit complexity increases
Solution Approach 1:
The pull-low switch shares the gate line infrastructure with the existing pixel circuit, utilizing the same gate line capacitance and transistor gate structure. This multi-functional approach allows the same gate line to serve both as the drive signal line during the high period and as the discharge path during the low period, reducing the need for completely separate circuitry.
Solution Approach 2:
The pull-low switch uses the existing gate line capacitance as its own discharge target, and the gate signal itself serves as one of the control inputs (along with the pull-low signal) to the pixel transistor. The circuit components serve multiple purposes: the gate line capacitance stores charge during the high period and is discharged during the low period, while the transistor gate both receives the drive signal and controls the pixel operation.
Data Source
AI summary
A display panel and a pixel circuit thereof are provided. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixel circuits. Each of the pixel circuits is coupled to corresponding gate line and data line. Each of the pixel circuits includes a first gate line and a pull-low switch. The first gate line is coupled to a control terminal of a driving transistor, and provides a first gate signal to drive the driving transistor during a driving time period. The pull-low switch pulls low the first gate signal to a reference low voltage according to a second gate signal on a second gate line when the driving time period finishes.