Pixel Circuit Reset Mechanism for Display Afterimage Reduction
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Solution Overview
Problem
Display panels experience instantaneous afterimage due to inconsistent drive current generation when switching between different grayscales, resulting in poor display effects, caused by insufficient reset of drive transistors leading to varying gate-source voltages and carrier trapping states.
Innovation Solution
A pixel circuit design that includes a data write module, a first reset module, and a drive transistor, where a constant first voltage signal is applied to the drive transistor's electrode and a reset voltage signal is applied to its gate at a first reset stage, ensuring consistent initial states for grayscale switching, thereby reducing afterimage and improving display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drive transistor is not fully reset before grayscale switching, then the circuit operation is simple and fast, but the gate-source voltage varies and carrier trapping states become inconsistent, causing instantaneous afterimage and poor display effect
Solution Approach 1:
The patent applies preliminary action by performing a reset operation on the drive transistor before the grayscale switching occurs. Specifically, a reset signal is applied to the gate of the drive transistor at a reset stage prior to the data write stage, ensuring that the gate-source voltage and carrier trapping states are standardized in advance. This preliminary reset action prevents instantaneous afterimage by eliminating residual charges and ensuring consistent initial conditions for subsequent grayscale display, thereby improving display reliability without adding complex operational procedures.
2Reliability
If a reset operation is performed at the first reset stage, then the afterimage is reduced and display effect is improved, but the driving process becomes more complex with additional control stages
Solution Approach 1:
The patent implements periodic action by incorporating a regular reset stage into the periodic driving cycle of the pixel circuit. The driving process is divided into distinct periodic stages: a first reset stage where a reset signal is applied to the gate, followed by a data write stage where data voltage is written. This periodic reset action occurs at the beginning of each frame or sub-frame cycle, ensuring that the drive transistor is consistently reset before each grayscale display sequence. By integrating the reset operation as a periodic component of the existing driving cycle rather than an ad-hoc intervention, the patent reduces instantaneous afterimage while maintaining a systematic and manageable driving process structure.
3Reliability
If the gate-source voltage is not standardized during grayscale switching, then the circuit operation is simpler without additional reset signals, but carrier trapping and releasing become inconsistent, causing brightness variation and afterimage
Solution Approach 1:
The patent applies preliminary action by standardizing the gate-source voltage through a reset signal applied at the first reset stage before grayscale switching occurs. The reset signal sets the gate voltage to a predetermined level, ensuring that the gate-source voltage is standardized in advance. This preliminary standardization of gate-source voltage ensures consistent carrier trapping and releasing behavior during subsequent grayscale switching operations, preventing brightness variation and instantaneous afterimage. By performing this standardization action beforehand, the patent improves brightness consistency while maintaining straightforward grayscale switching operations.
Data Source
AI summary
A pixel circuit, a driving method thereof, and a display device. The pixel circuit includes a data write module, a first reset module, a drive transistor, and a light-emitting module. The data write module is configured to apply a constant first voltage signal inputted from a data signal terminal to a first electrode of the drive transistor at a first reset stage; the first reset module is configured to apply a reset voltage signal inputted from a reset signal terminal to a gate of the drive transistor at the first reset stage; and the data write module is configured to apply a data voltage signal inputted from the data signal terminal to the gate of the drive transistor at a data write stage.