Pixel Circuit Layout for Shared Scanning of Tunable Circuits
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Solution Overview
Problem
Conventional electronic devices with tunable circuits on non-rectangular substrates face wiring and transistor layout difficulties, leading to inefficient operation due to different tunable characteristics.
Innovation Solution
The electronic device includes a pixel circuit with a scan transistor, a de-multiplexer transistor, a bias transistor, and a storage capacitor, allowing adjacent tunable circuits to share scan lines and reduce the number of scan lines and transistors, enabling efficient driving and selective scanning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each tunable circuit is assigned separate scan lines and transistors, then each circuit can be independently controlled, but the number of scan lines and transistors increases, leading to layout difficulties and reduced efficiency
Solution Approach 1:
Multiple tunable circuits are grouped into electronic units that share common scan lines and transistors. Specifically, multiple tunable circuits within the same electronic unit share a common scan line and common control transistors, reducing the total number of scan lines and transistors while maintaining independent control through shared resource allocation.
Solution Approach 2:
The shared scan lines and transistors serve multiple tunable circuits simultaneously. The common scan line and control transistors are designed to universally control multiple circuits within an electronic unit, allowing one set of components to perform the function that would otherwise require separate components for each circuit.
2Adaptability or versatility
If tunable circuits with different tunable characteristics are distributed on non-rectangular substrate, then circuit functionality is achieved, but wiring and transistor layout become difficult and driving efficiency decreases
Solution Approach 1:
The substrate is divided into multiple electronic units, each containing a specific number of tunable circuits (e.g., two circuits per unit). This segmentation allows circuits with different tunable characteristics to be organized into manageable groups, simplifying the wiring and transistor layout within each unit while accommodating the overall non-rectangular substrate shape.
Solution Approach 2:
The patent organizes tunable circuits into a two-dimensional array structure with row and column arrangements, where circuits are grouped in electronic units. This dimensional organization provides a systematic layout approach that simplifies wiring patterns and transistor placement, making manufacturing easier while supporting diverse tunable characteristics across the substrate.
Data Source
AI summary
An electronic device is provided. The electronic device includes a plurality of electronic units. Each of the plurality of electronic units includes a pixel circuit and a plurality of tunable circuits. The plurality of tunable circuits is coupled to the pixel circuit. The pixel circuit includes at least one scan transistor a plurality of de-multiplexer transistors, a plurality of bias transistors, and a storage capacitor. The plurality of de-multiplexer transistors is coupled to the at least one scan transistor. The plurality of bias transistors is coupled to the plurality of de-multiplexer transistors. The storage capacitor is coupled to a data line through the at least one scan transistor.