Pixel Circuit Shielding Layout for Precise Low-Power Display Control
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Solution Overview
Problem
Existing display devices face challenges in high integration and power consumption due to the increasing number of thin-film transistors (TFTs) required for precise control of display elements.
Innovation Solution
A display device design that includes a pixel circuit with a first and second thin-film transistor, each with a semiconductor layer and a gate electrode, and a shielding layer structure to enhance display quality and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of TFTs is increased to precisely control display elements, then control precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The gate electrode is divided into multiple gate electrodes (first gate electrode and second gate electrode), each independently controlling different regions of the semiconductor layer. This segmentation allows precise control of display elements while maintaining a manageable number of TFT structures, resolving the contradiction between control precision and device complexity.
Solution Approach 2:
The patent introduces a vertical stacking dimension by placing the first and second gate electrodes at different heights (different layers), with the first gate electrode on a lower layer and the second gate electrode on an upper layer. This three-dimensional arrangement enables independent control of channel regions without requiring additional planar TFTs, thus improving control precision while limiting device complexity.
2Measurement precision
If the number of TFTs is increased to precisely control display elements, then control precision is improved, but power consumption increases
Solution Approach 1:
By segmenting the gate control into multiple independent gate electrodes, each controlling specific channel regions, the patent enables selective activation of different transistor regions. This reduces unnecessary power consumption in inactive regions while maintaining precise control, resolving the contradiction between control precision and power consumption.
Solution Approach 2:
Different gate electrodes can apply different voltages to different regions of the semiconductor layer, creating local control zones. This allows power-efficient operation by activating only the necessary regions for current display requirements, rather than uniformly powering all TFTs, thus reducing overall power consumption while maintaining precise local control.
3Manufacturing precision
If shielding layers are added to improve display quality, then display quality is improved, but device complexity increases
Solution Approach 1:
The shielding function is merged with existing structural layers. The first shielding layer is integrated with the gate insulating layer structure, and the second shielding layer is combined with the gate electrode assembly. This merging approach provides shielding functionality without adding completely separate shielding structures, thus improving display quality while limiting the increase in device complexity.
Solution Approach 2:
The gate insulating layer serves multiple functions: electrical insulation between the gate electrode and semiconductor layer, and shielding against electrical interference. By making the insulating layer also function as a shielding layer, the patent improves display quality through better interference protection without requiring additional dedicated shielding layers, thus limiting complexity increase.
Data Source
AI summary
A display device includes a pixel circuit disposed on a substrate, and a display element on the pixel circuit. The pixel circuit includes a first thin-film transistor comprising a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, a second thin-film transistor comprising a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer being connected to the first semiconductor layer and the first gate electrode, a first shielding layer overlapping the second semiconductor layer, and a second shielding layer overlapping the second semiconductor layer and stacked on the first shielding layer.