Display Panel Pixel Circuit Layout for Lower Signal Delay
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Solution Overview
Problem
Existing display panels face challenges due to transistors with a large width-to-length ratio, leading to increased design complexity, electrode overlap, and signal delay, which affects the display effect.
Innovation Solution
The design of transistors with specific electrode configurations, including a first electrode with a wider sub-portion and a second electrode with a narrower sub-portion, reduces parasitic capacitance and resistance, enhancing the response speed and display effect by optimizing the layout and connection of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistors with a large width-to-length ratio are used to drive light-emitting devices with large current, then the driving capability is improved, but the design difficulty of the layout increases and electrode overlapping occurs
Solution Approach 1:
The first electrode is divided into a first sub-portion and a second sub-portion with different widths. The second sub-portion has a smaller width than the first sub-portion, creating a segmented structure that reduces overlapping area with the second electrode while maintaining the overall large width-to-length ratio for sufficient driving capability.
Solution Approach 2:
Different portions of the first electrode have different widths to optimize local properties. The first sub-portion has a larger width to maintain driving capability, while the second sub-portion has a smaller width to reduce overlapping area and parasitic capacitance, applying local quality variation to resolve the contradiction.
2Power
If transistors with a large width-to-length ratio are used, then the driving capability is improved, but the load of driving signal lines increases causing signal delay
Solution Approach 1:
By segmenting the first electrode into sub-portions with different widths, the overlapping area with the second electrode is reduced. This decreases the parasitic capacitance and the load on driving signal lines, thereby reducing signal delay while maintaining adequate driving capability through the overall transistor geometry.
Solution Approach 2:
The width parameter of the first electrode is varied across different sub-portions. The second sub-portion has a reduced width parameter compared to the first sub-portion, which changes the local electrical characteristics to reduce parasitic capacitance and signal line load, addressing the signal delay issue.
3Speed
If electrode overlapping is reduced, then parasitic capacitance is minimized improving response speed, but the transistor area may increase
Solution Approach 1:
The first electrode employs local quality variation with different width portions. The second sub-portion has a smaller width to minimize overlapping area and parasitic capacitance, improving response speed, while the first sub-portion maintains adequate width to ensure sufficient driving capability without excessive area expansion.
Solution Approach 2:
The electrode design utilizes dimensional variation within the plane by creating sub-portions with different widths. This in-plane dimensional differentiation allows reduction of overlapping area for lower parasitic capacitance while maintaining overall transistor area within acceptable bounds through optimized geometry.
Data Source
AI summary
Provided are a display panel and a display device. The display panel includes a substrate, a pixel circuit and a light-emitting unit. The pixel circuit and the light-emitting unit are located on one side of the substrate. The pixel circuit includes a first node electrically connected to a first power line and a second node electrically connected to the light-emitting unit. The pixel circuit includes a first transistor coupled between the first node and the second node and including a first electrode including a first portion extending in a first direction and a second electrode including a second portion extending in a second direction intersecting with the first direction. The driving delay of the first transistor can be improved, and the layout structure of the pixel circuit can be simplified.