Display Panel Pixel Circuit Layout for High-Resolution Signal Routing
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Solution Overview
Problem
Existing display panels face challenges in achieving high resolution and display quality, particularly in mobility-based electronic devices such as head-mounted displays, due to limitations in component design and integration.
Innovation Solution
The display panel incorporates a complex network of conductive and semiconductor patterns arranged in specific directions and layers, including overlapping and branching structures, with semiconductor materials like silicon and oxide semiconductors, to enhance pixel circuit efficiency and reduce parasitic capacitance, thereby improving display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If components for driving display panels decrease in size to improve resolution, then display quality and resolution are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements nested capacitor structures where a first capacitor is formed within the same pixel region as a second capacitor. The first capacitor includes a first electrode pattern and second electrode pattern, while the second capacitor includes a third electrode pattern and fourth electrode pattern. These capacitors are arranged in overlapping and interleaved configurations, allowing both capacitors to coexist in a compact space without interfering with each other's electrical functions, thus achieving high resolution display with improved pixel circuit efficiency
Solution Approach 2:
The patent utilizes multi-layer conductor arrangements where conductive patterns are disposed at different vertical levels (first conductor pattern, second conductor pattern, third conductor pattern at different layers). This three-dimensional arrangement allows signal transmission paths to be optimized without increasing the horizontal footprint of the pixel, enabling higher resolution while maintaining manageable device complexity
Solution Approach 3:
The pixel circuit is divided into multiple functional segments with dedicated conductor patterns for different signal paths (first conductive line, second conductive line, third conductive line, fourth conductive line). Each conductor pattern serves specific electrical connection functions, allowing independent optimization of signal transmission and reducing parasitic capacitance effects, thereby improving overall display performance without excessive complexity
2Reliability
If conductor patterns are arranged in overlapping and branching structures to reduce parasitic capacitance, then signal transmission is optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent designs conductor patterns with predetermined overlapping regions and alignment features that are planned in advance. The first conductive pattern includes specific overlapping portions with the second conductive pattern, and connection portions are pre-positioned to ensure proper electrical connection. This preliminary design approach allows manufacturing processes to follow a clear blueprint, reducing the actual precision requirements during fabrication while maintaining signal transmission quality
Solution Approach 2:
The patent introduces connection patterns and overlapping conductor regions that act as intermediaries between different signal paths. These intermediary structures provide gradual transitions and multiple connection points, reducing the impact of alignment variations and manufacturing tolerances on overall signal transmission quality
Data Source
AI summary
A display panel includes first and second semiconductor patterns extending in a first direction, a first conductive pattern including a portion overlapping the first semiconductor pattern, a second conductive pattern including a line portion extending in a second direction and branch portions extending in the first direction and each overlapping the first conductive pattern, first and second conductive lines extending in the second direction, third and fourth conductive lines extending in the second direction, and overlapping the first and second conductive lines, respectively, a third conductive pattern including a first portion overlapping the third conductive line and a second portion overlapping the fourth conductive line, a fifth conductive line extending in the first direction, and including a portion overlapping the third conductive pattern, and sixth and seventh conductive lines extending in the second direction and electrically connected to the first semiconductor pattern and the second conductive pattern, respectively.