Pixel Circuit Layout for Low-Capacitance Signal Writing

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The increasing load capacitance of signal lines in active matrix display devices due to multiple transistors connected to each line leads to prolonged potential settlement times, making high-speed signal writing in pixel circuits difficult.

Innovation Solution

The implementation of a first and second pixel circuit configuration with a signal line connected through a first transistor, each pixel circuit including a light emitting element, a second transistor, and a third transistor connected to the signal line via the first transistor, reducing the load capacitance by using block transistors that are half the number of write transistors connected directly to the signal line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of transistors connected to the signal line increases, then the pixel circuit functionality is improved, but the load capacitance of the signal line increases

Engineering Contradiction:

Improvepixel circuit functionalityVSAvoidload capacitance

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The pixel circuits are divided into groups, with each group sharing a common first transistor connected to the signal line. This segmentation reduces the number of transistors directly connected to the signal line, thereby decreasing load capacitance while maintaining full pixel circuit functionality through the grouped architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple pixel circuits are merged into groups that share common transistors (first transistor for signal line connection, and potentially other control transistors). This merging reduces the total number of transistors connected to the signal line, decreasing load capacitance while preserving individual pixel circuit operations through shared control mechanisms.

Inventive Principle:

Principle #5Merging (Combining)

2Quantity of substance

If the load capacitance of the signal line increases, then more pixel circuits can be connected, but the potential settlement time increases

Engineering Contradiction:

Improvenumber of pixel circuitsVSAvoidpotential settlement time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

By segmenting pixel circuits into groups with shared first transistors, the effective load capacitance presented to the signal line is reduced. This segmentation allows more pixel circuits to be connected overall while maintaining faster potential settlement times, as each group presents a smaller capacitive load to the signal line.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The grouped transistor architecture acts as an intermediary between the signal line and individual pixel circuits. This intermediary structure reduces the direct capacitive burden on the signal line by consolidating connections through shared first transistors, thereby decreasing potential settlement time while enabling connection of more pixel circuits.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Quantity of substance

If the load capacitance of the signal line increases, then more pixel circuits can be connected, but the signal writing accuracy deteriorates

Engineering Contradiction:

Improvenumber of pixel circuitsVSAvoidsignal writing accuracy

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

Segmenting pixel circuits into groups with shared first transistors reduces the load capacitance on the signal line. This reduction in capacitance improves signal writing accuracy by minimizing signal degradation and settling time variations, while still allowing a large number of pixel circuits to be connected through the grouped architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The grouped transistor structure serves as an intermediary that buffers the signal line from the full capacitive load of all pixel circuits. This intermediary architecture maintains signal writing accuracy by reducing the effective capacitance seen by the signal line, enabling accurate signal distribution to numerous pixel circuits.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12614517B2Light emitting device, photoelectric conversion device, and electronic apparatus

Publication Date: 2026.04.28 CANON KK

AI summary

A light emitting device includes a first pixel circuit and a second pixel circuit, a signal line configured to supply a pixel signal to the first pixel circuit and the second pixel circuit, and a first transistor connected to the signal line. Each of the first pixel circuit and the second pixel circuit includes a light emitting element, a second transistor arranged on a path where a current for causing the light emitting element to emit light flows, and a third transistor connected to a control terminal of the second transistor. The third transistor of each of the first pixel circuit and the second pixel circuit is connected to the signal line via the first transistor.