Pixel Circuit With Test Transistor Paths for Frequency Flexibility

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Solution Overview

Problem

Existing display devices lack the ability to operate at various frequencies and effectively test the operation of internal circuits, which can lead to inefficiencies and potential defects.

Innovation Solution

A pixel configuration is introduced that includes specific transistor and capacitor connections, allowing for both normal and test modes of operation, enabling frequency flexibility and circuit testing through controlled scan signal activation sequences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional pixel configuration is used, then the structure is simple, but the device cannot operate at various frequencies and cannot test internal circuits

Engineering Contradiction:
Improvefrequency flexibilityVSAvoidcircuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The pixel circuit is designed to perform multiple functions: normal display operation and internal circuit testing. The test transistor and additional capacitors enable the circuit to switch between display mode and test mode, allowing frequency flexibility and circuit verification without requiring separate test hardware

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The test transistor and capacitors are pre-configured in the pixel circuit to enable future testing operations. The circuit is designed with built-in test paths that can be activated by controlling the gate electrode voltages, allowing internal circuits to be tested before final assembly or during manufacturing

Inventive Principle:
Principle #10Preliminary action

2Reliability

If no test mechanism is provided, then the circuit structure is simpler, but internal circuit operation cannot be tested

Engineering Contradiction:
Improvecircuit functionality verificationVSAvoidtransistor and capacitor connections
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The pixel circuit tests itself using its own components. The test transistor, when activated, allows voltage from the gate electrode to be delivered through the existing transistor and capacitor network back to the data line, enabling self-diagnosis of internal circuit functionality without external test equipment

Inventive Principle:
Principle #25Self-service

3Ease of operation

If the second scan signal is activated before the first scan signal, then testing can be performed, but the operation sequence becomes more complex

Engineering Contradiction:
Improvetest mode activationVSAvoidscan signal control sequence
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The circuit operates dynamically by changing the activation sequence of scan signals to switch between normal display mode and test mode. During testing, the second scan signal is activated before the first scan signal, which turns on the test transistor in a specific sequence to enable voltage delivery through the test path, allowing flexible operational modes through signal timing control

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12400564B2Pixel and display device
Publication Date: 2025.08.26 SAMSUNG DISPLAY CO LTD
  • US12400564B2 patent drawing
  • US12400564B2 patent drawing
  • US12400564B2 patent drawing

AI summary

A pixel includes a light emitting element, a first transistor including a first electrode electrically connected to a first voltage line, a second electrode electrically connected to the light emitting element, and a gate electrode connected to a first node, a second transistor including a first electrode connected to a data line, a second electrode, and a gate electrode connected to a first scan line, a third transistor including a first electrode electrically connected to the first node, a second electrode connected to the second electrode of the first transistor, and a gate electrode connected to a second scan line, and a test transistor including a first electrode connected to the first electrode of the first transistor, a second electrode electrically connected to the second electrode of the second transistor, and a gate electrode connected to the second scan line.