Pixel Circuit Transistor Layout for Storage Capacitor Stability

The patent applies dimensional change by transitioning from conventional planar layout to a three-dimensional stacked architecture. Reset transistors and threshold compensation transistors are positioned in different vertical layers, creating extended leakage paths through the vertical dimension while maintaining compact footprint. This spatial reconfiguration reduces leakage current impact on storage capacitors without proportionally increasing layout complexity.

The patent implements nesting by integrating multiple transistor components within overlapping or nested spatial regions. The reset transistors and threshold compensation transistors are positioned such that their active regions partially overlap or nest within each other's boundaries, allowing extended leakage paths to be formed within a compact structural envelope. This nesting approach reduces the overall area while achieving the desired leakage reduction.

The patent applies segmentation by dividing the pixel circuit into distinct functional modules with clearly defined spatial relationships. The reset sub-circuit, threshold compensation sub-circuit, and storage capacitor are separated into distinct regions with standardized connection interfaces. This modular segmentation enables simplified manufacturing processes while maintaining the extended leakage path configuration that reduces leakage current effects on the storage capacitor.

The patent implements preliminary action by pre-configuring the transistor layouts and connection paths during the design phase to inherently extend leakage paths. The reset transistors and threshold compensation transistors are positioned in advance to create elongated leakage paths that pass through multiple intermediate regions. This preliminary spatial configuration ensures that leakage current is naturally directed away from the storage capacitor without requiring additional active control mechanisms during operation.