Pixel Circuit Transistor Arrangement for Display Panel
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing organic electroluminescence (EL) light-emitting display devices face challenges in efficiently arranging component elements within a given pixel area due to the large number of transistors and capacitors required, leading to complex interconnections and space constraints.
Innovation Solution
The proposed solution involves a pixel circuit design with a specific arrangement of transistors and light-emitting elements, including first and second scan lines, data lines, and a power electrode line, where transistors are arranged diagonally and capacitors are strategically placed to optimize space usage, allowing for efficient transfer of signals and current within the pixel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional pixel circuit design with multiple transistors and capacitors is used, then the display can represent brightness gradations, but the component arrangement becomes complex and space-consuming
Solution Approach 1:
The patent combines multiple transistors (first transistor for data signal transfer, second transistor for current output, third transistor for selection signal) into a single pixel circuit unit with integrated control. The capacitors are strategically positioned to share space with transistor structures, merging storage and switching functions into a compact arrangement that reduces overall circuit complexity while maintaining brightness gradation capability
Solution Approach 2:
The patent arranges components in a two-dimensional layout optimized for space utilization, with capacitors positioned adjacent to transistor structures rather than in separate regions. This spatial reorganization in the planar dimension allows efficient packing of all necessary components (transistors and capacitors) within the pixel area without increasing interconnection complexity
2Measurement precision
If more transistors and capacitors are added to improve brightness control, then brightness gradation precision improves, but the pixel area required increases
Solution Approach 1:
The patent nests capacitor structures adjacent to transistor structures, with capacitors positioned in the spaces between and around transistor components. This nested arrangement allows the capacitor and transistor to share portions of the same physical space, reducing the total pixel area required while maintaining all necessary functions for precise brightness control
Solution Approach 2:
The patent optimizes the two-dimensional layout by arranging capacitors and transistors in an interdigitated pattern that maximizes space utilization. Components are positioned to minimize wasted space and reduce the overall bounding box area of the pixel circuit while preserving the multi-transistor architecture needed for brightness gradation
3Ease of operation
If transistors are arranged in a conventional linear fashion, then signal transfer is straightforward, but space utilization in the pixel area is inefficient
Solution Approach 1:
The patent employs asymmetric arrangement of transistors and capacitors, with the first transistor positioned adjacent to the first data line, the second transistor positioned for optimal current output, and the third transistor positioned for efficient selection signal reception. This asymmetric layout optimizes signal transfer paths while minimizing the total area occupied by the pixel circuit
Data Source
AI summary
A current pixel circuit of a display device includes a switching transistor which may be turned on in response to the current selection signal to transfer a data signal, a driving transistor for outputting a current corresponding to the data signal, and first and second transistors being turned on in response to the previous selection signal. In the display device, the gate electrodes of the switching transistor of a previous pixel and the first and second transistors of the current pixel are coupled to one scan line for transferring the previous selection signal. Accordingly, the transistors are arranged in the order of the switching transistor of the previous pixel and the first and second transistors of the current pixel on the scan line at an area between two adjacent data lines.