Pixel Circuit Voltage Holding for Low Power Display
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing liquid crystal display devices face challenges in maintaining display quality and reducing power consumption, especially in constant display modes, where lowering the refreshing frequency leads to flicker and reduced contrast, and the addition of memory parts and polarity reversion drive circuits decreases the aperture ratio and brightness.
Innovation Solution
A pixel circuit design that includes a display element, internal node, first and second switch circuits, and a control circuit to manage pixel data voltage, using a series circuit with transistors and diodes to control voltage holding and refreshing, allowing for multi-gradation displays without increasing the number of elements and signal lines, thereby maintaining aperture ratio and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the refreshing frequency is lowered in constant display mode, then power consumption is reduced, but display quality deteriorates due to flicker and reduced contrast
Solution Approach 1:
The pixel circuit performs preliminary voltage holding by maintaining the pixel data voltage in the pixel electrode through the auxiliary capacitive element during periods when the TFT is off. This preliminary action ensures that the display quality is maintained without requiring continuous refreshing, thereby reducing power consumption while preventing flicker and contrast degradation.
2Reliability
If memory parts and polarity reversion drive circuits are added to maintain display quality at low refreshing frequency, then display quality is improved, but aperture ratio decreases
Solution Approach 1:
The auxiliary capacitive element serves multiple functions: it holds the pixel data voltage during TFT off-periods, maintains display quality during constant display mode, and enables voltage stabilization without requiring separate memory parts. This multi-functionality allows the pixel circuit to maintain display quality while avoiding the aperture ratio reduction that would result from adding dedicated memory components.
Solution Approach 2:
The invention extracts the voltage holding function from the TFT and relocates it to the auxiliary capacitive element. By taking out this function from the active transistor and placing it in a passive capacitive element, the circuit maintains display quality without requiring the TFT to remain continuously on, thereby reducing power consumption without adding memory parts that would reduce aperture ratio.
3Reliability
If the TFT remains continuously on to maintain pixel data voltage, then display quality is maintained, but power consumption increases
Solution Approach 1:
The pixel circuit implements periodic action by turning the TFT on and off in synchronization with the scanning lines. During constant display mode, the TFT is turned off after the initial writing phase, and the auxiliary capacitive element maintains the voltage periodically. This periodic operation reduces power consumption compared to continuous operation while maintaining display quality through the voltage holding capability of the capacitive element.
Data Source
AI summary
A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively. The diode D1 has a rectifying function from the source line SL to the internal node N1.