Pixel Circuit Wiring Segmentation for Display Voltage Drop
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Solution Overview
Problem
Flat panel display devices face issues with brightness unevenness and increased power consumption due to wiring resistance, particularly in organic EL panels, where voltage drops along power source lines cause brightness variations and potential screen burning.
Innovation Solution
The solution involves configuring a bypass path within the pixel circuit's inner line path and splitting the power source bus with slits to reduce electric resistance, thereby minimizing voltage drops and brightness unevenness without altering the wiring material or increasing production costs. This is achieved by forming comb-shaped branch portions in the source and drain wiring patterns and positioning bypass wiring below contact holes to avoid reducing the transistor's surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wirings are extended in one direction with reduced transverse sectional area to decrease capacitance between wirings, then signal delay is inhibited and pixel surface area is increased, but wiring resistance increases causing brightness unevenness and power consumption increase
Solution Approach 1:
The pixel circuit wiring is segmented into multiple parallel line paths (first line path and second line path) that connect the same source and gate electrodes. This segmentation allows current to flow through multiple routes simultaneously, reducing the effective resistance of the wiring without requiring increased wiring width, thus maintaining low power consumption while ensuring adequate current supply to the light-emitting element
Solution Approach 2:
The invention introduces a multi-dimensional wiring configuration by creating parallel conduction paths at different spatial locations within the pixel circuit. Instead of simply widening the wiring in one dimension, the current is distributed across multiple dimensions through parallel line paths, effectively reducing resistance without increasing the transverse sectional area of individual wirings
2Loss of energy
If wiring resistance is reduced by increasing transverse sectional area of power source lines, then brightness unevenness and power consumption are reduced, but capacitance between wirings increases causing signal delay
Solution Approach 1:
The high-capacitance wiring is segmented into multiple parallel line paths with smaller individual cross-sectional areas. This segmentation reduces the capacitance between wirings while maintaining the total conduction capacity through parallel paths, thereby reducing power consumption without causing signal delay
Solution Approach 2:
Multiple parallel line paths are merged to provide equivalent or superior conduction capacity compared to a single wide wiring. The combined effect of multiple narrow paths achieves low resistance while maintaining low capacitance, resolving the trade-off between power consumption and signal transmission speed
3Loss of energy
If bypass path is configured using additional wiring layers or contact holes, then wiring resistance is reduced, but device complexity and manufacturing cost increase
Solution Approach 1:
The existing source and gate wiring structures in the pixel circuit are made multi-functional by configuring them to serve both their original control functions and as bypass paths for current supply. This universal usage of existing structures reduces wiring resistance without adding complex additional layers or contact holes, maintaining manufacturing simplicity while achieving low power consumption
Solution Approach 2:
The pixel circuit's own wiring structures (source and gate lines) are utilized to provide the bypass path function, eliminating the need for separate dedicated bypass wiring. The existing wiring serves dual purposes: controlling the transistor and providing low-resistance current paths, thereby reducing device complexity while lowering power consumption
Data Source
AI summary
A flat panel display device includes a circuit board (110) that has formed thereon a plurality of power source lines (210) arranged in parallel, a power source bus (220) to which the plurality of power source lines (210) are connected, and a plurality of pixel circuits (240) each having an inner line path (66) connected to one of the power source lines (210). The display device also includes a plurality of light-emitting elements, each driven by a transistor provided in a corresponding one of pixel circuits (240). The inner line path (66) of each pixel circuit (240) provides a bypass path with respect to the power source line (210) connected thereto and part of the wiring for the transistor of the pixel circuit (240).