Pixel Clock Regeneration With Drift Feedback for Stable Synchronization
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Solution Overview
Problem
Existing methods for regenerating a pixel clock signal in wireless network transmission, such as using PLL components, face challenges in maintaining synchronization and stability, particularly in handling transient clock variations and frequency adjustments, which limits their robustness and requires additional buffering.
Innovation Solution
A device comprising first and second drift means to determine time differences between reference and local clock signals, with an adjustable clock generator and adjustment unit to continuously adjust the pixel clock signal based on these differences, ensuring accurate synchronization and stability through phase-locked loop adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLL components are used for regenerating pixel clock signal, then synchronization can be maintained, but the system requires additional buffering and has limited robustness against transient clock variations
Solution Approach 1:
The patent implements dynamic adjustment of the pixel clock signal by continuously measuring frame rate drift and adjusting the clock frequency in real-time. This dynamic approach allows the system to adapt to transient variations without requiring robust buffering, as the clock signal itself is being actively corrected to maintain synchronization.
Solution Approach 2:
The system employs feedback mechanisms by measuring the frame rate drift between source and display nodes and using this information to adjust the pixel clock frequency. This closed-loop control enables the system to maintain synchronization stability without relying on excessive buffering, as the feedback continuously corrects any drift.
2Measurement precision
If frequency adjustments are applied to PLL input reference, then output clock synchronization can be improved, but significant output clock cycle alterations are observed
Solution Approach 1:
The patent applies local quality by making adjustments only where necessary - specifically adjusting the pixel clock frequency based on measured drift while leaving the rest of the system operation unchanged. This localized adjustment approach allows precise frame rate drift compensation without causing widespread clock cycle alterations throughout the system.
Solution Approach 2:
The system changes parameters dynamically by adjusting the pixel clock frequency based on measured drift values. Rather than making fixed or aggressive adjustments, the parameter changes are proportional to the actual measured drift, allowing accurate compensation while maintaining overall clock stability.
3Reliability
If phase step adjustment is applied to output clock, then synchronization can be achieved, but unstable output frequency occurs during clock edges transitions
Solution Approach 1:
The patent implements smooth dynamic transitions by continuously adjusting the pixel clock frequency rather than applying abrupt phase steps. This dynamic adjustment approach maintains output frequency stability during transitions, as the clock frequency evolves gradually based on measured drift rather than jumping discontinuously.
4Device complexity
If low buffering architecture is used, then device complexity is reduced, but the system cannot tolerate frequency variations and transient clock variations
Solution Approach 1:
The system performs preliminary action by proactively adjusting the pixel clock frequency based on measured drift before synchronization errors accumulate. This preventive adjustment allows the system to maintain reliability with low buffering, as the clock is being corrected in advance rather than relying on buffers to absorb errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables more accurate compensation for frame rate drift between video source and display nodes, maintaining synchronization and stability of the pixel clock signal, even during transient phenomena, without the need for significant buffering.
Implementation Method 1
Some technical approaches use adjustable reference output clock generator components, based on PLL (Phase-Locked Loop) architecture for synchronisation purposes. Such components produce an output signal locally which maintains some pre-defined phase and frequency proportionalities relative to an input reference signal.
Data Source
AI summary
A method and device regenerating a pixel clock signal, the method comprising, and the device being configured for: determining a first drift value D1 representative of a first time difference between a reference clock signal RC and a local clock signal LC based on a local pixel clock signal LPC; adjusting the local pixel clock signal LPC according to an adjustment command to provide a regenerated pixel clock signal RPC; determining a second drift value D2 representative of a second time difference between the reference clock signal RC and a regenerated clock signal based on the regenerated pixel clock signal RPC; and providing the adjustment command to the adjustable clock generator 32; 132; 316 for adjusting the local pixel clock signal LPC, wherein the adjustment command is based on the difference between the determined first and second drift values.