Digital Pixel Clock Generation Circuit Jitter Elimination
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Solution Overview
Problem
Existing digital pixel clock generation circuits for displays face challenges with jitter and frequency conversion accuracy due to loose timing signals from image sources, leading to reduced video quality and costly solutions like external phase locked loop circuits.
Innovation Solution
A digital pixel clock generation circuit that uses an independent clock source and a programmable digital waveform generation circuit with a digital to analog converter, providing a fine stepping granularity and large frequency range, along with phase correction, to generate a stable pixel clock for format conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external phase locked loop circuit is used to generate the pixel clock, then the clock generation function is achieved, but the cost increases and jitter characteristics deteriorate
Solution Approach 1:
The patent extracts the PLL functionality from an external separate circuit and integrates it within the display device itself. The PLL circuit is now part of the display device's internal architecture, allowing the display to generate its own pixel clock without relying on external timing signals from image sources, thereby eliminating jitter while reducing overall system complexity and cost.
Solution Approach 2:
The display device becomes self-sufficient by generating its own pixel clock through an internal PLL circuit driven by a crystal oscillator. This self-service approach eliminates dependency on external clock sources with poor timing characteristics, allowing the display to maintain accurate synchronization without incurring the costs and complexities of external PLL circuits.
2Adaptability or versatility
If the pixel clock locks to an incoming pixel clock from an image source, then frequency conversion is achieved, but jitter from the source is transferred to the output
Solution Approach 1:
The patent introduces an intermediary crystal oscillator between the incoming horizontal synchronization signal and the pixel clock generation process. The crystal oscillator provides a stable, jitter-free reference frequency that mediates the conversion process, allowing format conversion while preventing the transfer of jitter characteristics from the image source to the display output.
3Reliability
If an independent clock source is used, then jitter is eliminated, but frequency conversion accuracy may be limited
Solution Approach 1:
The patent employs a dynamic PLL circuit that can adjust its division ratios and multiplication factors to achieve precise frequency conversion. The PLL dynamically configures its internal counters and dividers based on the required output frequency, allowing accurate frequency matching while maintaining the stability benefits of an independent crystal oscillator source.
Data Source
AI summary
A digital pixel clock generation circuit receives image data and corresponding image presentation time information from at least one external image source. The digital pixel clock generation circuit includes an image presentation timing error determination circuit that produces desired pixel clock frequency control information, such as pixel output clock adjustment control information, based on a difference between an expected presentation time and an actual presentation image time information. A programmable digital waveform generation circuit is programmed based on the produced desired pixel clock frequency and has an input that is responsive to an independent clock source, that is independent from the clock source of the external image source. The programmable digital waveform generation circuit provides a digital representation of an independently generated desired pixel clock which is then output to a digital to analog converter (DAC).