Pixel Clock Generator Using PLL Frequency Multiplication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing pixel clock generators in digital television systems require large off-chip capacitors and have narrow bandwidth due to the generation of output signals with tens or hundreds of MHz using low-frequency horizontal sync signals, limiting their efficiency and circuit complexity.
Innovation Solution
A pixel clock generator utilizing a phase-locked-loop (PLL) circuit to generate a multi-phase oscillation signal with several GHz frequency from an oscillation signal of tens of MHz, synchronized with a horizontal sync signal, and adjusted using a frequency/phase adjusting circuit comprising a phase synchronizing circuit and a delay control circuit to produce a pixel clock without the need for off-chip capacitors, achieving a wide bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL circuit generates output signals with tens or hundreds of MHz using low-frequency horizontal sync signals, then the pixel clock can be generated, but the bandwidth becomes narrow and large off-chip capacitors are required
Solution Approach 1:
The patent changes the operating frequency parameter from low-frequency horizontal sync signals (tens of kHz) to high-frequency oscillation signals (tens of MHz). This parameter change enables the PLL circuit to generate pixel clocks with wide bandwidth without requiring large off-chip capacitors, thereby resolving the contradiction between reliable pixel clock generation and circuit complexity
Solution Approach 2:
The patent extracts and removes the off-chip capacitors from the traditional PLL circuit design. By using high-frequency oscillation signals instead of low-frequency horizontal sync signals, the circuit no longer requires large off-chip capacitors, simplifying the overall circuit structure while maintaining pixel clock generation functionality
2Reliability
If large off-chip capacitors are used in the PLL circuit, then the pixel clock can be generated with sufficient bandwidth, but the circuit complexity and chip area increase
Solution Approach 1:
The patent removes the off-chip capacitors from the circuit by changing the input signal frequency to tens of MHz. This extraction eliminates the need for large capacitive components, thereby reducing chip area while maintaining sufficient bandwidth for pixel clock generation
Solution Approach 2:
By changing the input signal frequency parameter from low-frequency (tens of kHz) to high-frequency (tens of MHz), the patent achieves wide bandwidth without requiring large off-chip capacitors, thus reducing the overall chip area while maintaining reliability
3Device complexity
If the PLL circuit uses high-frequency oscillation signals of tens of MHz, then the bandwidth increases and off-chip capacitors are omitted, but the phase synchronization with horizontal sync signal becomes more challenging
Solution Approach 1:
The patent applies preliminary phase adjustment by selecting appropriate bits from the multi-phase oscillation signal to synchronize with the horizontal sync signal before further processing. This preliminary synchronization action simplifies subsequent phase alignment operations despite the high-frequency input signal
Solution Approach 2:
The patent segments the multi-phase oscillation signal into individual bits, allowing selective use of specific bits for synchronization with the horizontal sync signal. This segmentation approach makes phase synchronization more manageable by breaking down the complex high-frequency signal into discrete, controllable components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the generation of a pixel clock with a wide bandwidth, omitting the need for off-chip capacitors and simplifying the circuit structure, while allowing for efficient analog-digital conversion and phase adjustment, thereby improving the performance and efficiency of digital television systems.
Implementation Method 1
a phase-locked-loop (PLL) circuit configured to generate, from an oscillation signal having a first frequency of tens of MHz, a multi-phase oscillation signal having a second frequency of several GHz
Implementation Method 2
a delay control circuit configured to frequency-divide the first oscillation signal to generate a second oscillation signal, and adjust a phase of the second oscillation signal
Data Source
AI summary
A pixel clock generator is provided. The pixel clock generator includes a phase-locked-loop (PLL) circuit that generates, from an oscillation signal having a first frequency of tens of MHz, a multi-phase oscillation signal having a second frequency of several GHz; and a frequency/phase adjusting circuit that synchronizes the multi-phase oscillation signal with a horizontal sync signal to generate a first oscillation signal, frequency-divides the first oscillation signal to generate a second oscillation signal, and adjusts a phase of the second oscillation signal to generate the pixel clock.