Pixel Clock Generator Using Multiphase Frequency-Divided Signals
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Solution Overview
Problem
Digital televisions face challenges in generating a reliable pixel clock signal for converting analog image signals to digital, particularly in handling multiple frequency phases and synchronizing horizontal synchronization frequencies effectively.
Innovation Solution
A method and apparatus for a pixel clock generator (PCG) that generates N clock signals with different phases, frequency-divides them to produce M signals with varying phases, and uses a pixel clock signal modulator to create a pixel clock signal based on selected frequency-divided signals, incorporating a voltage-controlled oscillator, frequency-divided multiphase signal generating circuit, and feedback mechanisms to adjust the control voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple frequency-divided clock signals with different phases are generated to improve pixel clock signal reliability, then the PCG structure becomes more complex
Solution Approach 1:
The PCG is divided into multiple functional modules: a voltage-controlled oscillator that generates N clock signals, a frequency-divided multiphase signal generating circuit that creates M frequency-divided clock signals, and a pixel clock signal modulator that selects and combines signals. This segmentation allows each module to perform a specific function, improving reliability through modular design while managing complexity through functional separation.
Solution Approach 2:
The system dynamically selects at least two frequency-divided clock signals from the M available signals based on required pixel clock frequencies. The pixel clock signal modulator can switch between different combinations of frequency-divided signals, providing adaptability to different operating conditions while maintaining a fixed underlying structure, thus improving reliability without permanently increasing complexity.
2Manufacturing precision
If N clock signals with different phases are generated and frequency-divided to produce M signals, then accurate analog-to-digital conversion is achieved, but design and testing costs increase
Solution Approach 1:
The frequency-divided multiphase signal generating circuit serves multiple functions: it frequency-divides the N clock signals, generates M different phase signals, and provides selectable outputs for different pixel clock frequencies. This multi-functionality reduces the need for separate circuits for each function, thereby reducing design and testing costs while maintaining conversion accuracy.
Solution Approach 2:
The system changes the frequency and phase parameters of the clock signals through the frequency-divided circuit and modulator. By adjusting which frequency-divided signals are selected and combined, the system can achieve accurate analog-to-digital conversion for different pixel clock frequencies without requiring separate hardware designs, thus reducing design and testing costs.
3Measurement precision
If feedback mechanisms are implemented to adjust control voltage for frequency synchronization, then horizontal synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
A feedback mechanism is implemented where the generated pixel clock signal is fed back to the voltage-controlled oscillator to adjust the control voltage. This feedback loop automatically synchronizes the pixel clock frequency with the horizontal synchronization frequency, improving measurement precision while using a relatively simple feedback path that does not significantly increase overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the PCG structure, reduces design and testing costs, and ensures accurate conversion of analog to digital image signals by effectively managing multiple frequency phases and synchronizing horizontal synchronization frequencies, enhancing the performance of digital television systems.
Implementation Method 1
a voltage controlled oscillator configured to generate N clock signals based on the control voltage signal, the N clock signals having different phases
Implementation Method 2
a frequency-divided multiphase signal generating circuit configured to generate M frequency-divided clock signals respectively having different phases, based on the N clock signals
Implementation Method 3
a pixel clock signal modulator configured to generate a pixel clock signal based on at least two selected ones of the M frequency-divided clock signals
Data Source
AI summary
A method of operating a pixel clock generator (PCG), the method including generating N clock signals according to a control voltage signal, the N clock signals having different phases and N being a natural number; generating M frequency-divided clock signals based on the N clock signals, the M frequency-divided clock signals having different phases and M being a natural number greater than N; and generating a pixel clock signal based on at least two selected ones of the M frequency-divided clock signals.