Array Substrate Common Wiring Network for Stable Pixel Aperture
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Solution Overview
Problem
The triple gate pixel driving structure in display panels experiences reduced pixel aperture ratio and transmittance, affecting light efficiency due to the increased complexity of common routing lines and data lines, which impacts the uniformity and stability of common voltage.
Innovation Solution
The array substrate design includes a common routing line with specific configurations, such as overlapping regions with pixel electrodes and dense network structures, to form stable overlapping capacitors and improve voltage uniformity, while minimizing interference with data lines and gate lines, thereby enhancing the aperture ratio and light efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If triple gate pixel driving structure is adopted to reduce data lines, then the number of data lines decreases, but the pixel aperture ratio and transmittance are reduced
Solution Approach 1:
The common routing line is designed to extend in both first direction (along gate lines) and second direction (along data lines), creating a two-dimensional routing network. This dimensional expansion allows the common voltage signal to reach pixel electrodes more efficiently without requiring additional data lines, thus reducing the data line count while maintaining pixel aperture ratio.
Solution Approach 2:
The common routing line serves multiple functions: it provides common voltage to pixel electrodes, forms overlapping capacitors for voltage holding, and reduces interference with data lines. This multi-functionality allows the system to achieve reduced data line count while maintaining display performance through a single versatile routing structure.
2Stability of the object's composition
If common routing line overlaps with pixel electrode to form capacitor, then voltage uniformity improves, but light efficiency is affected
Solution Approach 1:
The common routing line is positioned to overlap with specific regions of the pixel electrode where it forms capacitive coupling for voltage holding. The routing line is designed to overlap with edge regions rather than the central light-emitting area, ensuring that the capacitive function is achieved while minimizing impact on light transmission efficiency.
Solution Approach 2:
The common routing line acts as an intermediary structure that provides electrical coupling between the common voltage source and the pixel electrode. By forming an overlapping capacitor through controlled overlap with the pixel electrode, it enables voltage uniformity while the routing line's conductive material serves as the mediating element that transfers voltage without blocking light paths.
3Stability of the object's composition
If common routing line is arranged densely to stabilize voltage, then voltage stability improves, but interference with data lines increases
Solution Approach 1:
The common routing line is designed to maintain equipotential distribution by extending along both gate lines and data lines, creating multiple capacitive coupling points with pixel electrodes. This equipotential design stabilizes voltage across the display panel while the distributed routing structure reduces current density and electromagnetic interference with data lines compared to a concentrated dense routing approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design stabilizes common voltage, improves capacitance coupling, and reduces dark stripes, resulting in enhanced light efficiency and aperture ratio in display panels.
Implementation Method 1
overlapping regions with pixel electrodes and dense network structures, to form stable overlapping capacitors and improve voltage uniformity
Data Source
Figure 1~2A
Figure 2B~2C
Figure 2D~2E
AI summary
An array substrate, a display panel and a display apparatus. The array substrate comprises common wiring (5), comprising a first common wiring portion (51) and a second common wiring portion (52) which are distributed in sequence along a first direction (X); the first common wiring portion (51) extends along the first direction (X), and an orthographic projection of the first common wiring portion (51) onto the substrate (1) and an orthographic projection of a pixel electrode (4) onto the substrate (1) have an overlapping region; the second common wiring portion (52) extends along a second direction (Y), and an orthographic projection of the second common wiring portion (52) onto the substrate (1) is located at the periphery of a data line (3) between adjacent pixel electrodes (4); furthermore, the orthographic projection of the second common wiring portion (52) onto the substrate (1) and an orthographic projection of the pixel electrode (4) onto the substrate (1) have an overlapping region.