Pixel Comparator Circuit With Negative Capacitance Timing Stabilization
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Solution Overview
Problem
The imaging device described in Patent Document 1 experiences errors in inversion timing of the comparator due to shared current sources, leading to nonlinearity and deterioration of image quality.
Innovation Solution
The imaging device incorporates a load current source with two cascode-connected transistors and a negative capacitance circuit that applies the signal line voltage to a common connection node via a capacitive element without logic inversion, stabilizing the comparator's timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the comparator shares the load current source of the pixel circuit, then power consumption is reduced, but the drain voltage of the P-channel MOS transistor varies according to the pixel signal level, causing timing error in the comparison result inversion
Solution Approach 1:
The patent introduces a negative capacitance circuit as an intermediary component between the signal line and the load current source. This circuit includes a capacitor connected to the common connection node of the two cascode-connected transistors, which mediates the voltage variation by applying the signal line voltage to stabilize the drain voltage of the P-channel MOS transistor during comparison operations, thereby resolving the timing error without requiring a separate current source
Solution Approach 2:
The patent changes the electrical parameters at the critical node by introducing a negative capacitance effect through the capacitor connection. This modifies the voltage characteristics at the common connection node of the cascode transistors, stabilizing the drain voltage during the comparison process and eliminating the timing error while maintaining the shared current source configuration
2Measurement precision
If the drain voltage of the P-channel MOS transistor is stabilized, then inversion timing accuracy is improved, but additional circuit components are required
Solution Approach 1:
The negative capacitance circuit serves multiple functions simultaneously: it stabilizes the drain voltage during comparison operations, compensates for signal line capacitance effects, and maintains proper operating conditions for the cascode transistors. This multi-functionality achieves timing accuracy improvement without proportionally increasing circuit complexity
Solution Approach 2:
The capacitor in the negative capacitance circuit acts as an intermediary that provides voltage stabilization with minimal additional complexity. By connecting the capacitor to the common node of the cascode transistors, the circuit achieves precise timing control through a simple additive component rather than a complete circuit redesign
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces errors in inversion timing, improving image quality by maintaining consistent comparison results and reducing power consumption.
Implementation Method 1
a negative capacitance circuit connected to the signal line; in which the negative capacitance circuit applies a voltage of the signal line to a common connection node of the two transistors of the load current source via a capacitive element without logic inversion
Data Source
AI summary
The present disclosure provides an imaging device capable of suppressing, when an analog pixel signal is compared with a predetermined reference signal, an error in inversion timing of the comparison result. The imaging device according to the present disclosure includes: a load current source; a comparator that is provided between a signal line for transmitting an analog pixel signal read from a pixel and the load current source and compares the analog pixel signal with a predetermined reference signal; and a negative capacitance circuit connected to the signal line. The load current source has two cascode-connected transistors. The negative capacitance circuit applies a voltage of the signal line to a common connection node of the two transistors of the load current source via a capacitive element without logic inversion.