Pixel Compression Mechanism for Graphics Data Transfer Bottlenecks

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Solution Overview

Problem

The large magnitude of data transferred between rasterization and Hierarchical Z-buffer blocks during graphics processing slows down graphics processor performance due to limited wiring and power in buses coupling these blocks.

Innovation Solution

A pixel compression mechanism that encodes coverage information for mega pixel spans, transmitting fully covered and void spans in a single signal and only the actual pixel data for partially covered spans, thereby increasing throughput and reducing data transfer requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all pixel data is transferred between rasterization and Hierarchical Z-buffer blocks, then complete depth checking can be performed, but data transfer volume increases and slows down graphics processor performance

Engineering Contradiction:
Improvedepth checking accuracyVSAvoidgraphics processor performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the parameter of data representation by encoding pixel coverage information in a compressed format. Instead of transferring full pixel data for all spans, the system uses encoding schemes that represent coverage patterns more efficiently, reducing the amount of data that needs to be transferred while maintaining the ability to perform complete depth checking.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent creates a compressed representation or copy of the pixel coverage information that suffices for depth checking purposes. Rather than transferring the complete original pixel data, an encoded copy containing the essential coverage information is transferred, which is sufficient for the Hierarchical Z-buffer block to perform its depth checking function.

Inventive Principle:
Principle #26Copying

2Productivity

If data transfer bandwidth is increased to maintain performance with large data volumes, then graphics processor performance is maintained, but wiring complexity and power consumption increase

Engineering Contradiction:
Improvegraphics processor performanceVSAvoidwiring and power requirements
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent changes the parameter of data compression to reduce the volume of data transferred. By applying compression algorithms and encoding schemes, the system reduces the data transfer bandwidth requirements while maintaining graphics processor performance, thereby avoiding the need for increased wiring capacity and power consumption.

Inventive Principle:
Principle #35Parameter changes

3Loss of information

If uncompressed pixel data is transferred, then all pixel information is available for processing, but data transfer time increases and throughput decreases

Engineering Contradiction:
Improvepixel information completenessVSAvoiddata transfer time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent applies data compression and encoding techniques that reduce the size of pixel data while preserving the essential information needed for depth checking. This reduces data transfer time and increases throughput while maintaining the completeness of pixel information required for accurate depth testing operations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10430990B2Pixel compression mechanism
Publication Date: 2019.10.01 INTEL CORP
  • US10430990B2 patent drawing
  • US10430990B2 patent drawing
  • US10430990B2 patent drawing

AI summary

An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.