Pixel Electrode Contact Layout to Reduce Display Crosstalk
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Solution Overview
Problem
As display devices with shrinking pixel sizes experience increased capacitive coupling between pixel electrodes and signal lines, leading to crosstalk and degraded display quality, existing technologies face challenges in reducing parasitic capacitance while maintaining high pixel resolution and minimizing power consumption.
Innovation Solution
The configuration of the display device includes a transistor with an oxide semiconductor layer, a specific arrangement of transparent conductive layers, and a filling member to extend contact holes along the signal direction, reducing parasitic capacitance by maintaining the thickness of insulating layers and optimizing the distance between signal lines and electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to increase resolution, then pixel resolution is improved, but parasitic capacitance between pixel electrodes and signal lines increases causing crosstalk
Solution Approach 1:
The patent extends contact holes in the first direction (signal line direction) rather than only vertically, creating an elongated contact structure that bypasses the parasitic capacitance problem by changing the dimensional approach to electrode connection
Solution Approach 2:
The patent introduces a filling member as an intermediary substance within the extended contact hole, which serves as a conductive pathway that electrically connects the pixel electrode to the signal line while minimizing parasitic capacitance effects
2Measurement precision
If distance between pixel electrodes and signal lines is reduced, then pixel resolution is improved, but capacitive coupling increases leading to crosstalk
Solution Approach 1:
Instead of reducing horizontal distance which increases capacitive coupling, the patent extends the contact hole vertically and in the signal direction, utilizing the third dimension to maintain electrical connection while preserving horizontal spacing between electrodes and signal lines
3Object-affected harmful factors
If insulating layer thickness is reduced to minimize parasitic capacitance, then parasitic capacitance is reduced, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent compensates for the reduced insulating layer thickness by extending the contact hole in the horizontal direction along the signal line, utilizing dimensional substitution to maintain electrical connection reliability without requiring thick insulating layers
Data Source
AI summary
A display device including a plurality of pixels arranged in a matrix on a substrate along a first direction and a second direction intersecting the first direction, wherein each of the plurality of pixels includes a transistor, a first transparent conductive layer arranged over the transistor and electrically connected to the transistor, a first insulating layer arranged over the first transparent conductive layer, a second transparent conductive layer arranged in the first insulating layer and electrically connected to the first transparent conductive layer via an opening extending over the plurality of pixels arranged in line in the first direction, a filling member arranged over the second transparent conductive layer to fill the interior of the opening, a third transparent conductive layer arranged on the first insulating layer and the filling member, and a metal layer in contact with the third transparent electrode.