Pixel Structure With Crossing Scan And Data Lines
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Solution Overview
Problem
The reduction in pixel size for higher image resolution leads to increased parasitic capacitance, affecting the voltage on pixel electrodes and reducing the fill factor of pixel structures, making it difficult to maintain or improve the design.
Innovation Solution
The pixel structure design involves scan lines and data lines crossing the pixel electrodes, reducing parasitic capacitance and allowing the pixel electrodes to be closer to the edges, thereby increasing the fill factor by adjusting the spacing and overlapping areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the pixel size is reduced to increase image resolution, then the image resolution is improved, but the parasitic capacitance increases and the fill factor decreases
Solution Approach 1:
The patent changes the spatial arrangement from conventional adjacent/disjoint lines to crossing lines in different dimensions. Scan lines and data lines cross each other and cross the pixel electrode, transforming the two-dimensional planar arrangement into a three-dimensional crossing structure. This dimensional change allows lines to pass through each other's space, reducing overlapping area and parasitic capacitance while maintaining connectivity.
Solution Approach 2:
The patent inverts the conventional arrangement where scan and data lines are disposed on adjacent sides of the pixel electrode. Instead, the lines cross the pixel electrode, with one line entering from one side and exiting from the opposite side. This inversion of the spatial relationship reduces the overlapping area between conductive lines and the pixel electrode, thereby reducing parasitic capacitance.
2Measurement precision
If the pixel size is reduced to increase image resolution, then the image resolution is improved, but the fill factor of the pixel structure decreases
Solution Approach 1:
By implementing crossing lines in three-dimensional space, the patent allows the pixel electrode to extend closer to the edges of the pixel region. The crossing arrangement frees up space that would otherwise be occupied by adjacent scan and data lines, enabling the pixel electrode area to increase even as the overall pixel size decreases.
3Device complexity
If the scan line and data line are disposed on adjacent sides of the pixel electrode, then the structure is simple, but parasitic capacitance is generated between the pixel electrode and multiple lines
Solution Approach 1:
The patent inverts the conventional adjacent-side arrangement by having scan and data lines cross the pixel electrode from opposite sides. This inversion reduces the overlapping area between the conductive lines and the pixel electrode, directly reducing parasitic capacitance while maintaining the relative simplicity of the structure through the crossing configuration.
Solution Approach 2:
The crossing arrangement moves the line configuration from a two-dimensional adjacent layout to a three-dimensional crossing layout. This dimensional change allows the lines to pass through the pixel electrode's space rather than running parallel to it, reducing the overlapping area and parasitic capacitance without significantly increasing structural complexity.
4Measurement precision
If the pixel size is reduced, then the image resolution is improved, but the voltage on the pixel electrode is easily affected by adjacent scan lines and data lines
Solution Approach 1:
By inverting the conventional arrangement and having lines cross the pixel electrode rather than run adjacent to it, the overlapping area between conductive lines is reduced. This reduction in overlapping area decreases the parasitic capacitance coupling between the pixel electrode and scan/data lines, thereby improving voltage stability on the pixel electrode even at smaller pixel sizes.
Solution Approach 2:
The three-dimensional crossing arrangement reduces the spatial overlap between the pixel electrode and conductive lines compared to the two-dimensional adjacent arrangement. This reduced overlap decreases parasitic capacitance effects, isolating the pixel electrode voltage from interference by adjacent scan and data lines while maintaining high image resolution.
Data Source
AI summary
A panel and a pixel structure are disclosed and include a substrate, a scan line, a data line, and a pixel electrode. The scan line is disposed on the substrate and extends along a first direction. The data line is disposed on the substrate and extends along a second direction different from the first direction. The pixel electrode is disposed on the substrate, in which the scan line and/or the data line crosses the pixel electrode.