Pixel Structure Data Line Configuration for High Refresh Rate Displays
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Solution Overview
Problem
Conventional pixel driving methods for high refresh rates in display apparatuses, such as those used in virtual reality or mobile games, often result in poor display quality due to insufficient compensation for threshold voltage in OLED pixels or low pixel charging rates in LCD pixels.
Innovation Solution
A pixel structure with specific data line configurations and a method for driving sub-pixels, where (4n+1)th and (4n+2)th data lines are located on opposite sides of (2n+1)th columns, and (4n+3)th and (4n+4)th data lines are on opposite sides of (2n+2)th columns, with strategic connections to odd and even-numbered rows of sub-pixels, reducing coupling capacitance and improving data signal accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional pixel driving methods are used to achieve high refresh rates (90 Hz or 120 Hz), then the refresh rate is improved, but display quality deteriorates due to insufficient threshold voltage compensation or low pixel charging rates
Solution Approach 1:
The data lines are segmented into different groups (first group: (4n+1)th and (4n+2)th data lines, second group: (4n+3)th and (4n+4)th data lines) with different configurations. Odd-numbered and even-numbered rows of sub-pixels are driven by different data line groups, allowing optimized charging paths for different pixel rows to improve both refresh rate and display quality simultaneously
2Area of stationary object
If data lines are densely arranged to increase pixel density, then the area is reduced, but coupling capacitance between data lines increases causing signal accuracy to deteriorate
Solution Approach 1:
The patent introduces a new dimensional arrangement pattern for data lines where (4n+1)th and (4n+2)th data lines are positioned on opposite sides of (2n+1)th column sub-pixels, and (4n+3)th and (4n+4)th data lines are positioned on opposite sides of (2n+2)th column sub-pixels. This spatial arrangement in the column dimension reduces coupling capacitance between adjacent data lines while maintaining high pixel density in the overall display area
3Manufacturing precision
If data lines are positioned close together to increase resolution, then the area is reduced, but coupling capacitance between data lines increases leading to poor display performance
Solution Approach 1:
Different data lines are assigned different local functions and positions: (4n+1)th data lines connect to odd-numbered rows, (4n+2)th data lines connect to even-numbered rows, and similar patterns for (4n+3)th and (4n+4)th data lines. This local differentiation in data line positioning and connection patterns reduces coupling capacitance interference between adjacent data lines while maintaining high manufacturing precision for pixel arrangement
Data Source
AI summary
A pixel structure is disclosed. The pixel structure includes: a plurality of scanning lines; a plurality of data lines intersecting the plurality of scanning lines; and a plurality of sub-pixels which are located at respective intersections of the plurality of scanning lines and the plurality of data lines and are arranged in rows and columns. (4n+1)th and (4n+2)th data lines of the plurality of data lines are located on opposite sides of a (2n+1)th column of sub-pixels respectively. (4n+3)th and (4n+4)th data lines of the plurality of data lines are located on opposite sides of a (2n+2)th column of sub-pixels respectively. The (4n+2)th and (4n+3)th data lines of the plurality of data lines are located between the (2n+1)th column of sub-pixels and the (2n+2)th column of sub-pixels, where n is an integer greater than or equal to 0.