3D Pixel Disaggregation Backplane for Bezel-Free Display Optics
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Solution Overview
Problem
Existing semiconductor display devices are limited by the bezel surrounding the pixel array, which affects their optical form factor and performance, and there is a need for improved compute capability and optical performance without increasing costs.
Innovation Solution
The method involves 3D stacking of semiconductor layers, relocating memory, logic, and analog devices to different layers, with the digital elements on a more advanced technology layer and analog elements on a separate layer, allowing for reduced bezel size and improved optical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory, logic, and analog devices are integrated in the same plane as the pixel array, then device area is reduced, but optical form factor is degraded due to the surrounding bezel
Solution Approach 1:
The patent transitions from a 2D planar integration to a 3D stacked architecture, moving memory, logic, and analog devices to different vertical layers beneath the pixel array. This dimensional change eliminates the need for a surrounding bezel, improving optical form factor while maintaining compact device area.
Solution Approach 2:
The patent segments the device into distinct functional layers: a pixel array layer at the top and separate layers below containing memory, logic devices, and analog devices. This segmentation allows each component to be optimized independently and eliminates the bezel requirement.
2Ease of manufacture
If digital and analog devices are placed on the same layer, then manufacturing is simplified, but compute capability and optical performance are limited
Solution Approach 1:
The patent separates digital devices (memory and logic) from analog devices (current sources and pixel control circuits) into different layers. This segmentation allows each layer to be manufactured using optimized processes for its specific device type, improving overall optical performance while maintaining manufacturing feasibility through modular fabrication.
Solution Approach 2:
The patent applies different manufacturing qualities to different layers: the digital backplane layer uses advanced CMOS processes for high-speed digital operations, while the analog layer uses specialized processes optimized for precision current sources and pixel control, achieving superior overall performance.
3Device complexity
If all devices are integrated in a single layer, then device complexity is reduced, but compute capability and pixel performance are insufficient
Solution Approach 1:
The patent uses vertical stacking to increase compute capability without increasing lateral complexity. Multiple layers provide additional functional capacity (memory, logic, analog control) while the modular inter-layer communication maintains manageable system complexity.
Solution Approach 2:
The digital backplane layer serves multiple functions: it provides memory storage, logic processing, and control signal generation for the entire device. This multi-functionality increases compute capability while avoiding the need for separate dedicated layers for each function.
4Device complexity
If a bezel is used to surround the pixel array, then device structure is simplified, but optical performance and form factor are degraded
Solution Approach 1:
The patent extracts and removes the bezel structure entirely by relocating all supporting devices (memory, logic, analog circuits) to vertical layers beneath the pixel array. This extraction eliminates the optical obstruction caused by the bezel while the layered structure provides the necessary structural support.
Data Source
AI summary
A method for pixel disaggregation can include forming a first layer of semiconductor material, wherein the first layer of semiconductor material includes memory and logic devices of a semiconductor device and is configured as a digital backplane that controls a plurality of analog devices of the semiconductor device. The method can additionally include forming a second layer of semiconductor material stacked atop the first layer of semiconductor material, wherein the second layer of semiconductor material includes the plurality of analog devices of the semiconductor device and is configured generate a per-pixel bias in response to control by the digital backplane. Various other methods, systems, and computer-readable media are also disclosed.