Pixel Drive Circuit Node Setting for Display Quality
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Solution Overview
Problem
Conventional display panels face issues with display quality due to different gate potential transitions of drive transistors at different display gray scales, affecting the light-emitting device's performance.
Innovation Solution
The proposed pixel drive circuit includes a light-emitting device, a drive transistor, and two light-emitting control transistors. The first light-emitting control transistor transmits a first voltage signal to the second and third nodes during a node setting stage, ensuring consistent gate-source voltage of the drive transistor across different gray scales.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If conventional pixel drive circuit drives light-emitting device, then light emission is achieved, but gate potential transitions cause display quality degradation
Solution Approach 1:
The patent applies preliminary action by setting the potentials of the second and third nodes to a reference potential before the light-emitting stage through the first light-emitting control transistor. This preliminary potential setting ensures that gate potential transitions of the drive transistor are suppressed during light emission, thereby maintaining stable drive current and improving display quality without affecting light-emitting performance
Solution Approach 2:
The patent introduces an intermediary mechanism by using the first light-emitting control transistor as a mediator between the power supply and the second/third nodes. This intermediary transistor controls the potential setting process, ensuring that the reference potential is applied at the appropriate timing (before light-emitting stage) to suppress unwanted gate potential transitions while enabling stable light emission
Data Source
AI summary
A pixel drive circuit includes a light-emitting device electrically connected to a first power supply terminal and a second power supply terminal; a drive transistor having a gate electrically connected to a first node and a source and a drain electrically connected to second and third nodes; a first light-emitting control transistor having a source and a drain electrically connected to the first power supply terminal and the second node, and a gate configured to receive a first light-emitting control signal; and a second light-emitting control transistor having a source and a drain electrically connected to the third node and the light-emitting device, and a gate configured to receive a second light-emitting control signal. The first light-emitting control transistor is configured to transmit a first voltage signal supplied from the first power supply terminal to the second and third nodes at a node setting stage.