Pixel Driver Chip Test Architecture for High-Throughput Wafer Probing
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Solution Overview
Problem
Testing of pixel driver chip donor wafers for micro LED displays is inefficient due to the small size of the chips and the large number of chips per wafer, making traditional testing methods time-consuming and prone to yield losses from defective chips.
Innovation Solution
The implementation of design-for-test architectures that utilize temporary and permanent test structures, including a redistribution layer (RDL) for probing and polycide or doped region test routing, allows for simultaneous testing of multiple pixel driver chips within a reticle field, reducing testing time and ensuring only known good dies are integrated into displays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional testing methods are used on pixel driver chip donor wafers, then each chip can be tested individually, but the testing time becomes excessively long and productivity is low due to the small size and large number of chips per wafer
Solution Approach 1:
Multiple pixel driver chips are merged into a single reticle area and tested simultaneously as a group. The test structure includes multiple pixel driver chip areas within one reticle area, allowing parallel testing of multiple chips through a single probe card interface, thereby dramatically increasing testing throughput while maintaining individual chip test accuracy
Solution Approach 2:
The patent transitions from testing chips in isolation (one-dimensional approach) to testing multiple chips arranged in a two-dimensional reticle area simultaneously. By organizing chips in rows and columns within the reticle area and using corresponding row and column select lines, the system achieves high-throughput parallel testing across the wafer surface
2Productivity
If more test structures are added to enable simultaneous testing of multiple chips, then productivity increases, but device complexity and manufacturing complexity increase
Solution Approach 1:
The reticle area structure serves multiple functions: it defines the physical boundary for multiple chip areas, provides the framework for organizing test pads in rows and columns, and integrates with the probe card interface. This multi-functional design enables simultaneous testing of multiple chips without requiring separate complex test structures for each chip
Solution Approach 2:
The reticle area is segmented into multiple pixel driver chip areas with associated test pads arranged in systematic row and column patterns. This segmentation allows the test structure to be divided into manageable units that can be selectively activated through row and column select lines, enabling parallel testing while maintaining structural organization and reducing overall complexity
3Ease of operation
If temporary redistribution layer is used for testing, then testing access is improved, but additional manufacturing steps and process time are required
Solution Approach 1:
A temporary redistribution layer is introduced as an intermediary structure between the pixel driver chips and the probe card during testing. This layer provides enlarged test pad areas that are accessible by the probe card, solving the access problem caused by small chip sizes. The layer is formed temporarily for testing purposes and then removed, enabling easy probe access without permanent structural modification
Solution Approach 2:
The temporary redistribution layer is discarded after serving its testing function. The layer is formed to enable testing access, used for probing the pixel driver chips, and then removed before final chip packaging. This temporary structure provides the necessary test access while avoiding permanent complexity in the final product
Data Source
AI summary
Test structures and methods of testing pixel driver chip donor wafers are described. In an embodiment, a redistribution layer is formed over a pixel driver chip donor wafer and probed to determine known good dies, followed by removal of the RDL. In other embodiments, test routing is formed in the pixel driver chip using a polycide material or doped region in the semiconductor wafer.