Pixel Driving Circuit Transistor Layout for AMOLED
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Solution Overview
Problem
The width-to-length ratio of the channel of the pixel driving thin film transistor in AMOLED displays is difficult to simultaneously reduce the current of the organic light emitting diode and increase the charging rate of the gate, and the large number of driving thin film transistors occupies significant space, hindering high pixel density designs.
Innovation Solution
A pixel driving circuit with a specific configuration of transistors and capacitors, where the first and second driving transistors are connected in series, and the width-to-length ratios of certain transistors are optimized to balance current reduction and charging rate enhancement, along with a layout structure that reduces transistor area and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the width-to-length ratio (W/L) of the channel of the driving thin film transistor is reduced by increasing the length of the channel, then the current of the organic light emitting diode is reduced, but the charging rate of the gate of the pixel driving thin film transistor decreases
Solution Approach 1:
The pixel driving circuit is divided into multiple functional modules including a data writing module (first driving transistor and second driving transistor in parallel), a holding module (third driving transistor), and a light emission module (fourth driving transistor). This segmentation allows each module to be optimized independently - the data writing module uses parallel transistors for high charging rate, while the fourth driving transistor uses increased channel length for current reduction, resolving the contradiction between charging rate and current control.
Solution Approach 2:
The circuit employs dynamic switching between different transistor configurations during different phases of operation. During the data writing phase, the parallel connection of first and second driving transistors provides high charging rate. During the light emission phase, the fourth driving transistor with optimized W/L ratio controls the current. This dynamic operation allows the system to achieve both high charging rate and low current simultaneously at different time points.
2Reliability
If the number of driving thin film transistors in the pixel driving circuit is increased to improve functionality, then the charging rate and current control are enhanced, but the occupied area increases
Solution Approach 1:
The first driving transistor and second driving transistor are connected in parallel to form a data writing module, merging their current paths to achieve both high charging rate and threshold voltage compensation. The gate electrodes of these transistors are connected to the same control signal line, further reducing the number of control lines needed. This merging approach enhances reliability while minimizing area occupation.
Solution Approach 2:
The pixel driving circuit is designed with multi-functional transistors that perform multiple roles. For example, the first driving transistor serves both as a data writing transistor and as part of the threshold voltage compensation mechanism. The third driving transistor functions as both a holding element and a switching element. This multi-functionality reduces the total number of transistors needed, thereby reducing the occupied area while maintaining reliable current control.
Data Source
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AI summary
The present disclosure provides a pixel driving circuit, a driving method thereof, and a layout structure of a transistor. The pixel driving circuit includes a storage capacitor, a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, a first driving transistor, a second driving transistor, and an organic light emitting diode. The layout structure of the transistor includes a circuit node and an active layer connected to the circuit node; the active layer includes: a first active layer, a second active layer, and a third active layer; a first source connected to the first active layer, a drain connected to the second active layer, and a second source connected to the third active layer; a first gate, a second gate, and a third gate corresponding to the first active layer, the second active layer, and the third active layer respectively; and a gate pattern composed of the first gate, the second gate, and the third gate being located above the circuit node and the active layer.