Pixel Electrode Layout to Cut Parasitic Capacitance in Displays
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Solution Overview
Problem
As liquid crystal display devices increase in size and resolution, the need for high-speed operation and higher on-state current in transistors leads to increased parasitic capacitance, causing signal transmission delays, display unevenness, and higher power consumption.
Innovation Solution
The display device incorporates a semiconductor film with In, M (aluminum, gallium, yttrium, or tin) oxides, featuring a structure with overlapping regions between electrodes and a gate insulating film to reduce parasitic capacitance, and includes a signal line design that minimizes overlap with capacitor wiring, optimizing transistor and capacitor configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels is increased to achieve larger size and higher definition, then the display resolution is improved, but the parasitic capacitance between wirings increases causing signal transmission delay
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar wiring layout to three-dimensional stacked wiring structure. Multiple wiring layers are arranged vertically, allowing signal lines to pass through different levels without horizontal overlap, thereby reducing parasitic capacitance while maintaining high pixel density for 8K resolution displays
Solution Approach 2:
The patent segments the wiring system into multiple independent layers, separating signal transmission paths vertically. This segmentation allows each wiring layer to be optimized independently, reducing interference and parasitic capacitance between adjacent wirings while supporting the increased pixel count required for high-definition displays
2Reliability
If high-speed driving is implemented to reduce image sticking and improve display quality, then the display quality is improved, but the power consumption increases
Solution Approach 1:
The patent changes the driving parameters by implementing multi-phase gate control with optimized timing sequences. The gate voltage is applied in multiple phases rather than continuously, reducing the overall power consumption while maintaining high-speed response characteristics needed to prevent image sticking and ensure display quality
3Speed
If the transistor is designed for high on-state current to support high-speed operation, then the operation speed is improved, but the parasitic capacitance increases causing signal transmission delay
Solution Approach 1:
The patent uses three-dimensional stacked transistor structures where the active channel is formed vertically. This allows high on-state current through increased channel area without expanding the planar footprint, and the vertical stacking reduces parasitic capacitance between source/drain regions and gate, enabling high-speed operation without signal transmission delay
Data Source
AI summary
A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film. The signal line intersects with the scan line, the first electrode is electrically connected to the signal line, the first electrode has a region overlapping with the scan line, the second electrode faces the first electrode, the third electrode faces the first electrode, the first pixel electrode is electrically connected to the second electrode, the second pixel electrode is electrically connected to the third electrode, the semiconductor film is in contact with the first electrode, the second electrode, and the third electrode, and the semiconductor film is provided between the scan line and the first electrode to the third electrode.