Pixel Electrode and Data-Line Layout for Brightness Stability
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Solution Overview
Problem
Existing electronic device designs with double gate lines face issues such as display brightness instability, color mixing, and bright or dark streaks due to parasitic capacitance and polarity inversion effects, which affect display quality.
Innovation Solution
The electronic device incorporates a layout design with a first substrate, gate lines, an electrode layer, and a data line, where the data line is overlapped with specific portions of the electrode layer to minimize parasitic capacitance and polarity inversion effects, and adjusts driving waveforms to synchronize and extend charging times for improved display stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a layout design with double gate lines is adopted to reduce data driving circuit usage, then device complexity is reduced, but display brightness stability deteriorates due to parasitic capacitance and polarity inversion effects
Solution Approach 1:
The patent extracts and removes the problematic data line from the region where it creates parasitic capacitance with the gate line. By repositioning the data line away from the gate line's projection area, the harmful capacitive coupling is eliminated, resolving the brightness stability issue while maintaining the simplified double gate line structure.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the gate line and the data line. This insulating layer acts as a barrier that prevents direct capacitive coupling between the gate line and data line, thereby eliminating parasitic capacitance effects while allowing both lines to coexist in the layout.
2Area of stationary object
If the data line is positioned close to the gate line to save space, then device area is reduced, but harmful parasitic capacitance increases causing bright or dark streaks
Solution Approach 1:
The patent extracts the data line from the problematic region where it overlaps with the gate line's projection. By repositioning the data line to a location where it does not create parasitic capacitance with the gate line, the harmful effect is removed while maintaining compact device area through optimized layout.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary barrier between the gate line and data line. This insulating layer prevents direct capacitive coupling, allowing the data line to be positioned closer to the gate line without creating harmful parasitic capacitance, thus maintaining compact device area.
3Reliability
If driving waveforms are extended to synchronize charging times, then display stability is improved, but update rate decreases
Solution Approach 1:
The patent applies preliminary action by extending the charging time period in advance to ensure complete charging of the pixel electrodes before the next frame begins. This preliminary charging action eliminates display instability and eliminates the need for additional synchronization adjustments, achieving stable display without further compromising update rate.
Data Source
AI summary
An electronic device includes an electrode layer having a first-, second-and third-pixel electrodes in sequence, a metal layer having a first, second and third parts in sequence, and a data line. The first and second parts overlap a gap between the first-and second-pixel electrodes. The third part overlaps a gap between the second-and third-pixel electrodes. The data line overlaps a gap between the first and second parts. Along a direction, a minimum distance between the data line and the first part is less than a width of the first part, a minimum distance between the data line and the second part is less than a width of the second part, and a distance between a side edge of the first part overlapping the second-pixel electrode and a side edge of the second part overlapping the second-pixel electrode is greater than a width of the third part.