Pixel Electrode Layout for Lower Data-Line Parasitic Capacitance
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Solution Overview
Problem
Display devices face challenges in reducing parasitic capacitance between pixel electrodes and data lines, which affects display quality by causing deviations in pixel characteristics and luminance.
Innovation Solution
The design includes a specific arrangement of pixel circuit portions and data lines, where pixel electrodes overlap data lines in a plan view, with a conductive layer structure that includes capacitor electrodes connected to transistors, reducing parasitic capacitance and improving display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If pixel electrodes are arranged to overlap data lines, then parasitic capacitance between pixel electrodes and data lines increases, but this arrangement is necessary for compact pixel design
Solution Approach 1:
The patent applies local quality by making the second pixel electrode have a smaller area than the first pixel electrode. This localized reduction in electrode area specifically reduces the parasitic capacitance between the second pixel electrode and the data line, while maintaining the overlapping arrangement for compact design. The differential electrode sizing allows the structure to simultaneously achieve compactness and reduced parasitic effects in critical locations.
2Manufacturing precision
If parasitic capacitance between pixel electrode and data line is reduced, then display quality improves, but this requires complex electrode and circuit arrangements
Solution Approach 1:
The patent employs asymmetry by configuring the first and second pixel electrodes with different areas. The first pixel electrode has a larger area while the second pixel electrode has a smaller area. This asymmetric design allows differential control of parasitic capacitance for different sub-pixels, improving display quality by reducing luminance deviations while maintaining a relatively simple overall structure without requiring complex additional components.
3Object-affected harmful factors
If pixel circuit portions are arranged along a direction perpendicular to data lines, then parasitic capacitance is reduced, but this arrangement affects pixel density
Solution Approach 1:
The patent addresses the spatial arrangement by utilizing vertical stacking in the electrode configuration. The second pixel electrode is positioned to overlap the data line in the vertical dimension, while the first pixel electrode is positioned away from the data line. This three-dimensional arrangement allows both electrodes to be accommodated in a compact area, maintaining high pixel density while the overlapping configuration of the second electrode specifically reduces parasitic capacitance effects.
Data Source
AI summary
The present disclosure relates to a display device, and the display device according to an exemplary embodiment of the present inventive concept includes: a first pixel circuit portion including at least one transistor; a second pixel circuit portion including at least one transistor; a first pixel electrode electrically connected to the first pixel circuit portion; a second pixel electrode electrically connected to the second pixel circuit portion; a first data line electrically connected to the first pixel circuit portion; and a second data line electrically connected to the second pixel circuit portion, wherein the first data line and the second data line are arranged adjacent to each other along a first direction, and the second pixel electrode overlaps the first data line and the second data line in a plan view.