Pixel Unit Elevating Layer Reduces Via Hole Slope
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Solution Overview
Problem
In thin film transistor liquid crystal displays, the deep and sloped via holes in organic insulation layers lead to breakage of conductive materials and the Rubbing Mura phenomenon due to their large size and poor planarization, making it difficult to reduce the slope effectively.
Innovation Solution
The introduction of elevating layers below the via holes reduces the depth and slope of the via holes, ensuring better connection between the pixel and drain electrodes without increasing production costs or complexity, using unetched portions of the gate metal and active layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the organic insulation layer is increased to reduce coupling capacitance, then the insulation performance improves, but the via hole depth increases causing conductive material breakage and Rubbing Mura phenomenon
Solution Approach 1:
The patent introduces an elevating layer that adds a vertical dimension to the via hole structure. By forming this elevating layer at the bottom of the via hole, the effective depth of the via hole is reduced while maintaining the required insulation layer thickness, thereby improving planarization without compromising insulation performance
Solution Approach 2:
The elevating layer acts as an intermediary structure between the via hole and the underlying layers. It provides a platform that reduces the slope and depth of the via hole, preventing conductive material breakage and Rubbing Mura phenomenon while allowing the insulation layer to maintain its thickness for proper insulation
2Reliability
If the slope of the via hole is reduced to prevent conductive material breakage, then the reliability improves, but the via hole size must increase requiring more space
Solution Approach 1:
Instead of reducing the via hole slope by increasing the via hole size in the horizontal plane, the patent uses the vertical dimension by introducing an elevating layer. This approach reduces the effective depth and slope of the via hole without increasing the horizontal space required, thus maintaining reliability while preserving pixel unit density
3Reliability
If a thicker inorganic insulation layer is used to improve insulation, then the insulation performance improves, but the via hole depth increases causing similar problems
Solution Approach 1:
The patent changes the material parameter of the insulation layer from inorganic to organic material. Organic insulation layers can achieve the required insulation performance with greater thickness while allowing for better via hole planarization through the elevating layer structure, avoiding the problems associated with thick inorganic insulation layers
Data Source
AI summary
The present disclosure provides a pixel unit and a method for producing the same, an array substrate and a display apparatus. The pixel unit includes: a thin film transistor; an insulation layer formed at least on a drain electrode of the thin film transistor and formed therein with a via hole which extends through the insulation layer to expose the drain electrode of the thin film transistor below the insulation layer; a pixel electrode formed on the insulation layer and electrically connected to the drain electrode of the thin film transistor at the via hole; and at least one elevating layer formed below the via hole and located below a part of the drain electrode exposed from the via hole such that the exposed part has a height greater than the height of the parts of the drain electrode adjacent to the exposed part. The depth and slope of the via hole is reduced by adding the elevating layer below the via hole. The elevating layer may be made from the gate metal layer and/or the active layer that are not etched off in process without increasing any production cost and process difficulty.