Pixel Processing Engine Layout to Reduce SoC Memory Latency
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Solution Overview
Problem
Conventional accelerators in systems on a chip (SoCs) face constraints due to system latencies associated with memory reading and writing during single instruction, multiple data (SIMD) operations, particularly in robotic and autonomous systems, limiting the efficiency of computationally-intensive tasks like image processing.
Innovation Solution
Implementing a pixel processing engine (PPE) with a 2D array of processing elements that processes data independently of a common memory source and adjusts bit width, allowing for subdivided data processing across multiple elements, reducing memory bottlenecks and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional accelerators use a common memory source for data processing, then data access is simplified, but memory latency limits processing efficiency
Solution Approach 1:
The patent divides the processing system into multiple independent processing elements (PEs) arranged in a 2D array, where each PE has its own local memory. This segmentation eliminates the single memory bottleneck by distributing data storage across multiple local memory units, allowing parallel processing without centralized memory latency.
Solution Approach 2:
The patent transitions from a conventional 1D processor array to a 2D mesh array architecture. This dimensional change enables more efficient data routing and access patterns, where data can flow horizontally and vertically across the mesh, reducing access time and improving parallel processing throughput.
2Adaptability or versatility
If conventional accelerators use fixed bit width processing, then hardware design is simplified, but adaptability to different data scales is limited
Solution Approach 1:
The patent implements dynamically reconfigurable processing elements that can adjust their bit width and operational parameters based on the processing requirements. Each PE can be configured to handle different data types and precision levels, enabling the system to adapt to various application needs without hardware changes.
Solution Approach 2:
The processing elements are designed as universal, multi-functional units that can perform various operations (addition, multiplication, logic operations) at different bit widths. This universality allows a single PE design to handle diverse computational tasks, from low-precision sensor data to high-precision image processing.
3Productivity
If conventional accelerators process all data through centralized memory, then data management is simplified, but math-to-memory ratio is limited
Solution Approach 1:
The patent segments the memory architecture into multiple local memory units distributed across the processing elements. This segmentation allows each PE to access its own local memory directly, performing multiple mathematical operations on locally stored data before accessing external memory, thereby improving the math-to-memory ratio.
Solution Approach 2:
The patent introduces local memory units as intermediary storage between the processing elements and the main memory system. These local memories act as buffers that hold frequently accessed data, reducing the frequency of external memory accesses and improving computational efficiency.
Data Source
AI summary
In various examples, systems and methods are disclosed that relate to processing data using accelerators in a system on a chip. For example, a plurality of processing elements (PEs) can interconnect to form a processing engine, and a control system can control operation of the PEs based at least on the connections between the PEs. In some examples, the PEs can receive sub-inputs and transfer the sub-inputs to one or more other PEs to enable performance of the instructed operations. In examples, once the PEs complete the instructed operations, the sub-inputs can be transferred out of the processing engine.