Pixel Processing Engine Layout for Low-Latency Inter-Accelerator Transfers

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Solution Overview

Problem

Conventional processing accelerators face inefficiencies due to system latencies in memory access and constrained bit widths, limiting the performance of SIMD operations in robotic systems, particularly in automated vehicle operations.

Innovation Solution

Implementing a pixel processing engine with a 2D array of processing elements that allows independent data processing and adjustable bit width, reducing memory access latencies and improving communication between processing elements, especially for operations involving larger kernels and adjacent pixel values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional accelerators use common memory source for data processing, then data access is simplified, but memory access latencies increase and processing efficiency decreases

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidmemory access latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The system segments the memory architecture by providing each processing element with a dedicated local memory buffer instead of sharing a common memory source. This segmentation allows parallel data access across multiple processing elements without contention, reducing memory access latency and improving overall processing efficiency for SIMD operations.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If conventional accelerators use fixed bit width, then hardware design is simplified, but adaptability to different processing requirements is limited

Engineering Contradiction:

Improvebit width adjustabilityVSAvoidhardware configuration complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system implements dynamic bit width configuration for processing elements, allowing the bit width to be adjusted based on the specific processing requirements of different applications. This dynamic adaptability enables the accelerator to optimize performance for various data types and operations while maintaining a relatively simple hardware architecture through programmable control.

Inventive Principle:

Principle #15Dynamics

3Speed

If accelerators perform repeated reads and writes to system memory, then data consistency is maintained, but power consumption increases and processing speed decreases

Engineering Contradiction:

Improveprocessing speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The system performs preliminary action by pre-loading data into local memory buffers of processing elements before the actual processing operations begin. This allows processing elements to access data from their local buffers during SIMD operations without repeated reads and writes to system memory, significantly reducing power consumption and improving processing speed while maintaining data consistency.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20260037480A1Systems and methods for performing inter-accelerator data transfers

Publication Date: 2026.02.05 NVIDIA CORP

AI summary

In various examples, systems and methods are disclosed that relate to performing inter-accelerator data transfers. For example, an accelerator such as a pixel processing engine (PPE) can include multiple processing engines (PEs). The PEs can be arranged in a two-dimensional array and each PE can be configured to receive data in the registers of the PEs. The PEs can transfer data between registers of the same or different PEs. The PEs can also be configured to perform transfers and operations in sequence to perform complex functions such as filtering.