Pixel Fetch Request Interface for DRAM Access Overhead
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Solution Overview
Problem
Conventional DRAM access methods incur significant overhead due to non-consecutive memory location accesses, particularly in video encoding and decoding processes like AVC, where reference pixels can straddle multiple rows and banks, leading to inefficient burst transactions.
Innovation Solution
A pixel fetch request interface (PFRI) is introduced, which converts reference pixel requests into optimized memory access requests, grouping addresses to minimize overhead and allowing non-consecutive accesses by generating lists of DRAM word addresses that prioritize row access efficiency, using a memory access unit to handle pixel-related accesses and arbitrate requests efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional DRAM access methods are used for non-consecutive memory locations, then memory access requests can be processed, but significant overhead is incurred due to multiple pre-charge operations required for each row access
Solution Approach 1:
The patent segments the memory access request into two independent parts: a row address list that determines which rows need to be accessed, and a column address list that specifies the exact locations within those rows. This segmentation allows the system to batch multiple row accesses together, reducing the frequency of pre-charge operations and thereby reducing overall memory access overhead.
Solution Approach 2:
The patent performs preliminary actions by pre-calculating and organizing the row address list and column address list before actual memory access occurs. The system prepares the access request in advance, grouping consecutive row addresses together to enable burst transactions. This preliminary organization of access patterns allows the DRAM controller to optimize the actual memory access sequence, reducing redundant pre-charge operations.
2Productivity
If burst transactions are used for consecutive memory locations, then access efficiency is improved, but functions that access non-consecutive locations (like motion compensation in video decoding) cannot benefit from this optimization
Solution Approach 1:
The patent introduces dynamic adaptability by allowing the row address list and column address list to be generated flexibly based on the actual access pattern requirements. The system can dynamically adjust the grouping of row addresses and the mapping of column addresses to accommodate both consecutive and non-consecutive access patterns. This dynamic generation of access lists enables burst transactions to be optimized for consecutive accesses while still handling non-consecutive accesses efficiently through flexible address list construction.
Solution Approach 2:
The patent introduces an intermediary layer in the form of the row address list and column address list that mediates between the high-level memory access requests and the physical DRAM access operations. This intermediary structure allows the system to translate various access patterns (consecutive, non-consecutive, random) into an optimized sequence of row and column addresses, enabling burst transactions to benefit from both consecutive access patterns and flexible handling of non-consecutive patterns.
3Adaptability or versatility
If reference pixels are stored in memory in various ways to accommodate different video standards, then versatility is improved, but memory locations become non-consecutive and increase access overhead
Solution Approach 1:
The patent resolves the contradiction by adding a dimensional transformation layer through the row address list and column address list. Instead of directly mapping reference picture storage layouts to memory addresses, the system introduces an intermediate address translation dimension. This allows the same physical memory layout to support multiple reference picture storage conventions by translating between the abstract reference picture coordinates and the physical memory row-column addresses, thereby maintaining versatility while optimizing access patterns.
Data Source
AI summary
Presented herein are system(s) and apparatus for a memory access unit for accessing data for a module. The memory access unit comprises an output port for providing access requests for lists of addresses in a memory over a link to a memory controller.