Pixel Structure with Floating Metal Layer to Reduce Parasitic Capacitance
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Solution Overview
Problem
Conventional TFT-LCD pixel structures suffer from parasitic capacitance between metal layers, leading to signal distortion and degraded display quality due to overlapping metal layers.
Innovation Solution
A pixel structure is introduced with a patterned floating metal layer between the dielectric and semiconductor layers, forming parasitic capacitances in series to reduce the overall capacitance, comprising a substrate, first metal layer, dielectric layer, semiconductor layer, second metal layer, and pixel electrode, with the patterned floating metal layer partially overlapping the gate and source/drain, and a pad layer between the scan and data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the first metal layer and the second metal layer are partially overlapped to form the conventional pixel structure, then the device complexity is reduced and manufacturing is simplified, but parasitic capacitance is produced between the metal layers causing signal distortion and degraded display quality
Solution Approach 1:
A patterned floating metal layer is introduced as an intermediary between the first metal layer (gate and scan line) and the second metal layer (source/drain and data line). This intermediate layer is disposed between the dielectric layer and the semiconductor layer, with portions overlapping the gate and source/drain regions. The floating metal layer acts as a mediator that reduces the direct parasitic capacitance coupling between the first and second metal layers, thereby mitigating signal distortion while preserving the overlapping structure's manufacturing simplicity
Solution Approach 2:
The patent segments the capacitance coupling path by introducing the floating metal layer that divides the direct interaction between the first and second metal layers into multiple smaller capacitance elements. The floating metal layer is patterned to overlap only specific regions (gate and source/drain) rather than the entire area, effectively segmenting the parasitic capacitance into manageable portions that can be controlled and minimized
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, enhancing display quality and design tolerance by creating series capacitances that result in lower total capacitance, thereby improving signal transmission and panel design flexibility.
Implementation Method 1
the first metal layer 120 and the second metal layer 150 are partially overlapped, so as a parasitic capacitance is produced in the overlapped location thereof
Data Source
AI summary
A pixel structure comprises a substrate, a first metal layer, a dielectric layer, a semiconductor layer, a second metal layer, a patterned floating metal layer and a pixel electrode. The first metal layer, disposed on the substrate, comprises a gate and a scan line electrically thereto. The dielectric layer, overlapped by the semiconductor layer, is disposed on the substrate and overlapping the first metal layer. The second metal layer comprises a source/drain, disposed on the semiconductor layer and partially overlaps the gate, and a data line, electrically connects to the source and partially overlapped with the scan line. The pixel electrode electrically connects to the drain. Additionally, the patterned floating metal layer is disposed between the dielectric layer and the semiconductor layer, beneath the source/drain and partically overlapping the gate.