Pixel Transistor Gate Layout for Larger Display Channel Regions
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Solution Overview
Problem
Existing display devices face challenges in efficiently arranging transistors within a pixel, leading to suboptimal area utilization and reduced channel region size for transistors.
Innovation Solution
The display device incorporates a design where multiple transistors in each pixel are arranged such that their gate electrodes do not overlap in a specific direction, allowing for efficient placement and potentially increasing the total size of the channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate electrodes of transistors in different pixels are arranged to overlap in the first direction, then the pixel area utilization is reduced, but the manufacturing process is simpler
Solution Approach 1:
The patent extends the transistor gate electrode arrangement from a single-plane two-dimensional layout to a three-dimensional multi-layer configuration. By placing gate electrodes of different pixels on different layers (first layer and second layer) and connecting them through contact holes, the design achieves non-overlapping spatial arrangement that improves pixel area utilization while maintaining manufacturability through standardized multi-layer fabrication processes
2Length of stationary object
If transistors are arranged with overlapping gate electrodes, then the device structure is simpler, but the channel region size is reduced
Solution Approach 1:
The patent utilizes vertical layering to separate gate electrodes of adjacent pixels into different planes. This three-dimensional arrangement allows each transistor to maintain its full channel region dimensions without spatial interference from neighboring transistors, thereby increasing the effective channel region size while the multi-layer structure manages the added geometric complexity
Solution Approach 2:
The patent divides the gate electrode arrangement into segmented layers, with first gate electrodes on a first layer and second gate electrodes on a second layer. This segmentation allows independent optimization of each layer's transistor layout, enabling larger channel regions without requiring a completely redesigned monolithic structure
Data Source
AI summary
A display device which allows efficient arrangement of transistors within a pixel includes a plurality of pixels arranged adjacently along a first direction, a plurality of transistors disposed in each pixel and a light emitting element disposed in each pixel, and connected to at least one of a plurality of transistors in each pixel, wherein gate electrodes of corresponding transistors of different pixels, which are connected to the same signal line, are disposed so as not to overlap in the first direction.