Pixel Metal Grid Connection Through Buffer Dielectric Openings

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In back-illuminated CMOS image sensors, the metal grid formed in the pixel area is physically connected but not electrically connected to the underlying substrate and deep-trench fill structures, limiting the optimization of electrical performance.

Innovation Solution

A semiconductor device is fabricated with a substrate, trench fill structure, and a buffer dielectric layer that exposes portions of the substrate, allowing a metal grid layer to be directly electrically connected to the substrate and trench fill structures, thereby enhancing electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If the metal grid is separated from the underlying substrate by a buffer dielectric layer, then the optical performance is improved, but the electrical connection between the metal grid and substrate is lost

Engineering Contradiction:
Improveoptical performanceVSAvoidelectrical connection
Core Design Contradiction:
Illumination intensityVSReliability

Solution Approach 1:

The buffer dielectric layer is segmented to create localized openings, allowing the metal grid to maintain electrical connection with the substrate at specific points while remaining optically isolated in other areas. This segmentation resolves the contradiction by enabling both optical performance improvement and electrical connection preservation through spatial differentiation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buffer dielectric layer exhibits different properties in different regions: it provides electrical isolation in covered areas for optimal optical performance, while creating openings in specific locations to maintain necessary electrical connections. This local quality variation allows simultaneous achievement of both optical and electrical performance goals.

Inventive Principle:
Principle #3Local quality

2Stability of the object's composition

If the metal grid is physically connected to the substrate, then the structural stability is improved, but the electrical performance cannot be optimized

Engineering Contradiction:
Improvestructural stabilityVSAvoidelectrical performance
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The buffer dielectric layer is divided into regions with and without openings, enabling the metal grid to have both physical support from the substrate (through openings) and electrical isolation (through dielectric coverage). This segmentation allows structural stability and electrical performance optimization to coexist.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buffer dielectric layer acts as an intermediary between the metal grid and substrate, providing mechanical support while controlling electrical interaction. By strategically placing openings in this intermediary layer, the system achieves both structural stability and optimized electrical performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20230378232A1Semiconductor device
Publication Date: 2023.11.23 WUHAN XINXIN SEMICON MFG CO LTD
  • US20230378232A1 patent drawing
  • US20230378232A1 patent drawing
  • US20230378232A1 patent drawing

AI summary

A semiconductor device is disclosed. The semiconductor device includes: a substrate defining a pixel area; a trench fill structure formed in the substrate in the pixel area; a buffer dielectric layer formed over a surface of the substrate in the pixel area, the buffer dielectric layer defining a first opening, which at least exposes a portion of the substrate surrounding the trench fill structure; and a metal grid layer formed on the buffer dielectric layer, the metal grid layer filling the first opening to at least directly contact with and electrically connect to the exposed portion of the substrate. The present invention provides a technical solution that brings the metal grid layer into electrical connection with the exposed portion of the substrate, thus allowing optimization or amelioration of the semiconductor device's electrical performance.