Digital Pixel Imager Dual Bloom Storage Capacitors Cascode Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In legacy analog imagers, particularly infrared imagers, the shrinking pixel size leads to a disproportionate reduction in well capacitor size, which limits the Signal-to-Noise Ratio (SNR), and existing in-pixel ADC circuits face inefficiencies due to reset events that can contribute to accuracy loss and increased complexity.
Innovation Solution
A digital pixel circuit utilizing two integration capacitors and cascode transistors, where charge is accumulated on one capacitor until a threshold is reached, then transferred to the second capacitor, allowing continuous integration during resets and reducing reset event duration, with switches controlling the flow and subtraction of charge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pixel size is reduced to increase resolution, then imaging resolution is improved, but well capacitor size decreases leading to reduced Signal-to-Noise Ratio
Solution Approach 1:
The patent divides the well capacitor function into two separate capacitors (first integration capacitor and second integration capacitor). This segmentation allows the photo-charge integration to continue during reset operations, as charge can be accumulated in one capacitor while the other is being reset, thereby maintaining SNR performance even in smaller pixels.
2Measurement precision
If reset events are performed frequently to maintain integration accuracy, then integration accuracy is improved, but reset event duration increases reducing productivity
Solution Approach 1:
The patent enables continuous photo-charge integration by using two capacitors in parallel. While one capacitor is undergoing reset, the other continues to accumulate charge. This continuity eliminates the interruption in integration that would normally occur during reset events, thereby maintaining both accuracy and speed.
Solution Approach 2:
The circuit performs preliminary charging of one capacitor while the other is being reset. This allows the system to prepare the next integration capacitor in advance, so that when a reset is needed, the integration can seamlessly switch to the pre-charged capacitor, minimizing reset duration and maintaining productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances SNR by reducing the duration and frequency of reset events, leading to smaller, more power-efficient imagers with improved resolution and accuracy, suitable for higher resolution and cryo-cooled infrared applications.
Implementation Method 1
Charge from a photo-diode is accumulated over an integration capacitor
Implementation Method 2
Charge is accumulated on the first integration capacitor until a voltage on the first integration capacitor exceeds the reference voltage
Data Source
AI summary
An integration capacitor network for connection to a photo-current source includes: an input; a first path connected between the input and a reset voltage, the first path including a first integration capacitor and a first cascode transistor, the first cascode transistor coupled between the input and the first integration capacitor; and a second path connected between the input and the reset voltage, the second path including a second integration capacitor and a second cascode transistor, the second cascode transistor coupled between the input and the second integration capacitor. Gates of the first and second cascode transistors are connected to a reference voltage and charge is accumulated on the first integration capacitor until a voltage on the first integration capacitor exceeds the reference voltage and then charge is accumulated on the second integration capacitor.