Image Sensor Pixel Isolation Fences for Narrow Gate Spacing
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Solution Overview
Problem
The existing semiconductor processing technologies for image sensor pixel cells with global shutters are limited by minimum polysilicon-to-polysilicon design rules, which restrict the close spacing of gate electrodes, affecting shutter efficiency, dark current, white pixels, and image lag, and require additional processing steps to prevent light leakage.
Innovation Solution
The implementation of isolation fences between the gates of image sensor pixel cells, fabricated to minimum line width design rule limitations, allows for narrower spacings between the transfer, storage, and output gates, improving transfer efficiency and reducing image lag without the need for double polysilicon processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the spacing between gate electrodes is decreased to improve shutter efficiency and reduce image lag, then performance is improved, but the minimum polysilicon-to-polysilicon design rule limits how closely spaced the gates can be
Solution Approach 1:
The patent introduces isolation fences as vertical structures extending from the substrate upward between adjacent gate electrodes. This adds a vertical dimension (z-axis) to the spacing problem, allowing horizontal gate spacing to be reduced while maintaining electrical isolation through the vertical fence structure. The isolation fences create three-dimensional separation that resolves the two-dimensional planar spacing constraint imposed by polysilicon design rules.
Solution Approach 2:
The isolation fences act as intermediary structures between adjacent gate electrodes. These fences serve as mediating elements that provide electrical isolation and prevent light leakage between gates, enabling the gates to be placed closer together than would otherwise be permitted by design rules. The isolation fences transfer the isolation function from a horizontal separation requirement to a vertical barrier structure.
2Object-affected harmful factors
If the spacing between gate electrodes is decreased to reduce dark current and prevent light leakage, then image quality is improved, but additional processing steps are required
Solution Approach 1:
The isolation fences serve multiple functions simultaneously: they provide electrical isolation between gates, block light leakage between adjacent pixel cells, and enable reduced gate spacing. By consolidating these multiple isolation requirements into a single structural element, the patent reduces the need for separate processing steps that would otherwise be required to address each function individually.
Solution Approach 2:
The patent merges the electrical isolation function and optical isolation function into a single isolation fence structure. Instead of requiring separate layers or structures for electrical isolation and light blocking, the isolation fence combines both functions, thereby reducing overall device complexity and processing steps while achieving both dark current reduction and light leakage prevention.
3Productivity
If the spacing between gate electrodes is decreased to improve transfer efficiency, then pixel cell performance is improved, but the polysilicon design rule constraints are violated
Solution Approach 1:
The isolation fences extend vertically from the substrate between the gate electrodes, introducing a vertical dimension to the isolation scheme. This allows the horizontal spacing between gates to be reduced for improved transfer efficiency while the vertical fence structure maintains design rule compliance by providing the required isolation through the z-axis rather than relying solely on horizontal separation.
Solution Approach 2:
The isolation fences are placed locally between specific gate electrodes where spacing reduction is needed, rather than uniformly increasing spacing across the entire device. This localized approach allows transfer efficiency to be improved in critical regions while maintaining design rule compliance, with the fence structures providing targeted isolation only where required for close-spaced gates.
Data Source
AI summary
A pixel cell includes a photodiode, a storage transistor, a transfer transistor and an output transistor disposed in a semiconductor substrate. The transfer transistor selectively transfers image charge accumulated in the photodiode from the photodiode to the storage transistor. The output transistor selectively transfers the image charge from the storage transistor to a readout node. A first isolation fence is disposed over the semiconductor substrate separating a transfer gate of the transfer transistor from a storage gate of the storage transistor. A second isolation fence is disposed over the semiconductor substrate separating the storage gate from an output gate of the output transistor. Thicknesses of the first and second isolation fences are substantially equal to spacing distances between the transfer gate and the storage gate, and between the storage gate and the output gate, respectively.