Pixel Transistor Layout to Minimize Capacitive Coupling
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Solution Overview
Problem
As display devices with higher resolutions increase, capacitive coupling between data lines and gate electrodes of pixel transistors becomes a significant issue affecting display quality.
Innovation Solution
The design includes specific transistor configurations and layering of gate electrodes and conductive patterns on insulating layers, along with shielding members to minimize capacitive coupling, and uses oxide and poly-silicon transistors to manage signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If higher resolution is implemented in display devices, then display quality is improved, but capacitive coupling between data lines and gate electrodes increases causing display quality degradation
Solution Approach 1:
The harmful capacitive coupling effect is extracted and eliminated by removing the gate electrode from direct proximity to the data line. The gate electrode is repositioned to overlap only with the semiconductor layer, separating it from the data line path and eliminating the parasitic capacitance between gate and data line that degrades display quality at high resolutions.
Solution Approach 2:
The gate electrode is repositioned in the vertical stacking dimension rather than extending horizontally near the data line. By placing the gate electrode in a different spatial dimension (overlapping the semiconductor layer vertically while the data line runs horizontally in another layer), the capacitive coupling is minimized while maintaining the necessary electrical functions.
2Manufacturing precision
If pixel circuitry is made more complex to achieve higher resolution, then display quality is improved, but leakage currents and flicker phenomena increase
Solution Approach 1:
The transistor type parameter is changed from conventional silicon-based transistors to oxide semiconductors. This material parameter change fundamentally alters the electrical characteristics, achieving ultra-low leakage currents (on the order of 10^-21 to 10^-24 A) while maintaining the complex pixel circuitry needed for high resolution, thereby eliminating flicker phenomena.
Solution Approach 2:
The pixel circuit employs a composite approach by using oxide semiconductor materials in specific transistor configurations. The oxide semiconductor layer is integrated with conventional transistor structures, creating a hybrid system that leverages the low-leakage properties of oxide semiconductors while maintaining the functional complexity required for high-resolution display.
3Reliability
If oxide transistors are used to reduce leakage current, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The oxide semiconductor layer serves multiple functions simultaneously: it acts as the active channel layer for low-leakage transistor operation, provides gate electrode overlap region for capacitance control, and functions as part of the overall pixel circuit structure. This multi-functionality reduces the need for separate components and simplifies the manufacturing process despite the advanced material used.
Data Source
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AI summary
A display device may include a plurality of pixels each including a light emitting element. A first scan line and a second scan line, are disposed in each of the pixels. A data line is disposed in each of the pixels. A power line is disposed in each of the pixels. A reference voltage line is disposed in each of the pixels. A first transistor controls a current of the light emitting element. A second transistor is connected between the data line and a first gate electrode of the first transistor. A third transistor is connected between the reference voltage line and a first electrode of the first transistor. A fourth transistor is connected between the power line and a second electrode of the first transistor. The fourth transistor may be a transistor of a type different from that of the first to third transistors.