Pixel-Based Layout Rule Checking for Curvilinear IC Edges
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Solution Overview
Problem
Existing optical lithography technologies face challenges in accurately transcribing critical dimensions of circuit patterns onto substrates, especially as feature sizes approach the resolution limit of exposure tools.
Innovation Solution
The method involves performing pixel-based rule checking on layouts with curvilinear shapes, using multiple processing threads to examine individual pixels and dynamically generate edges to check for rule violations such as spacing and width checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional optical lithography is used to manufacture circuit patterns, then the manufacturing process can handle larger feature sizes, but the manufacturing precision deteriorates as critical dimensions approach the resolution limit of exposure tools
Solution Approach 1:
The patent segments the rule checking process into pixel-level operations, where each pixel along curvilinear edges is independently processed by separate processing threads. This segmentation enables parallel computation and maintains precision for small features by examining each pixel's contribution to the overall pattern accuracy.
Solution Approach 2:
The patent transitions from traditional contour-based rule checking to a pixel-based approach, adding a dimensional perspective by treating the layout as a rasterized image grid. This dimensional change allows for more accurate representation of curvilinear edges and improves transcription accuracy for sub-resolution features.
2Manufacturing precision
If pixel-based rule checking is performed on curvilinear shapes, then the manufacturing precision for curvilinear edges is improved, but the device complexity increases due to multiple processing threads and dynamic edge generation
Solution Approach 1:
The system performs self-service by automatically generating edges from pixel data without requiring external input or manual definition. Each processing thread independently generates edges for its assigned pixels, and the system self-manages the parallel computation coordination, reducing the need for complex external control mechanisms.
Solution Approach 2:
The pixel-based rule checking system serves multiple functions: it performs spacing checks, width checks, and edge generation simultaneously across all curvilinear shapes in the layout. The same processing infrastructure handles different rule types and shape complexities uniformly, reducing overall system complexity despite the enhanced capabilities.
3Productivity
If traditional rule checking methods are used, then the device complexity is lower, but the productivity decreases due to inability to efficiently handle curvilinear edges
Solution Approach 1:
The patent performs preliminary rasterization of the layout into pixels before rule checking begins. This preliminary action converts continuous curvilinear shapes into discrete pixel representations, enabling subsequent parallel processing and improving productivity by avoiding repeated contour calculations during the rule checking phase.
Solution Approach 2:
The patent replaces traditional mechanical contour-based rule checking with a computational pixel-based system. By substituting the mechanical approach of tracing and measuring continuous curves with computational analysis of discrete pixel arrays, the system achieves higher productivity through parallel processing while managing complexity through algorithmic efficiency.
Data Source
AI summary
Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).