Active Matrix Pixel Layout for Flicker-Resistant Oxide TFT LCDs
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Solution Overview
Problem
Parasitic capacitance in liquid crystal display devices using oxide semiconductor TFTs leads to fluctuations in pixel potential, causing flicker and reducing display quality, particularly during low-frequency driving.
Innovation Solution
The layout of pixel regions is designed to control the balance between own and other source parasitic capacitances by forming additional parasitic capacitances using the oxide semiconductor layer, and arranging pixel sets to cancel out brightness changes, maintaining high pixel aperture ratio and light utilization efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If low-frequency driving is performed to reduce power consumption, then power consumption is reduced, but pixel potential fluctuates due to parasitic capacitance causing flicker
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitance into a beneficial one by intentionally forming additional parasitic capacitance between the pixel electrode and oxide semiconductor layer. This additional capacitance compensates for the potential fluctuation caused by the original parasitic capacitance during pause periods, thereby reducing flicker while maintaining low-frequency driving operation
Solution Approach 2:
The patent creates a composite capacitance structure by combining the original parasitic capacitance (between pixel electrode and source bus line) with an additional parasitic capacitance (between pixel electrode and oxide semiconductor layer). This composite capacitance system balances the electrical characteristics to minimize potential fluctuation during low-frequency driving
2Speed
If oxide semiconductor TFTs are used instead of amorphous silicon TFTs, then operating speed is improved, but parasitic capacitance increases causing pixel potential fluctuation
Solution Approach 1:
The patent changes the electrical parameters of the pixel structure by introducing an additional parasitic capacitance element. This parameter change balances the overall capacitance characteristics, compensating for the potential instability caused by the high-speed oxide semiconductor TFT's inherent parasitic capacitance
3Use of energy by moving object
If pixel aperture ratio is increased to improve light utilization efficiency, then light utilization efficiency is improved, but control over parasitic capacitance balance becomes more difficult
Solution Approach 1:
The oxide semiconductor layer serves multiple functions: it acts as the active layer for the TFT transistor operation and simultaneously functions as one electrode for the additional parasitic capacitance. This multi-functionality allows the structure to maintain high aperture ratio while providing the necessary capacitance balance without requiring separate dedicated capacitance structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces flicker occurrence and improves display quality by balancing parasitic capacitances, ensuring effective low-frequency driving without compromising aperture ratio or light efficiency.
Implementation Method 1
the oxide semiconductor layer in the oxide semiconductor TFT of the each of the pixel regions overlaps the pixel electrode of a first adjacent pixel region of the plurality of pixel regions with the insulating layer interposed therebetween
Data Source
AI summary
An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.