Photoelectric Conversion Pixel Layout for Faster Focus Signal Readout
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Solution Overview
Problem
Solid-state imaging devices experience reduced reading speed and complex signal processing when performing horizontal addition of pixel signals, particularly when pixels used for focus detection are involved, leading to increased load and processing complexity.
Innovation Solution
A photoelectric conversion device with a pixel array where pixels are arranged such that the first and second signal lines intersect, allowing for parallel signal processing circuits to handle signals efficiently, reducing parasitic capacitance and signal processing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixels for focus detection are arranged in a pixel array and horizontal addition of pixel signals is executed, then focus detection capability is improved, but reading speed is lowered and signal processing becomes complicated
Solution Approach 1:
The pixel array is segmented into different regions: imaging pixels for image capture and focus detection pixels for autofocus. These pixels are spatially separated and connected to different signal lines, allowing independent processing paths that prevent focus detection from bottlenecking the overall reading speed.
Solution Approach 2:
Different signal lines act as intermediaries between the pixel array and signal processing circuits. By routing focus detection pixel signals through dedicated signal lines separate from imaging pixel signals, the system enables parallel processing that maintains reading speed while achieving focus detection capability.
2Measurement precision
If pixels for focus detection are arranged in a pixel array and horizontal addition of pixel signals is executed, then focus detection capability is improved, but signal processing complexity increases
Solution Approach 1:
The signal processing system is segmented into separate processing circuits: one for imaging pixels and another for focus detection pixels. This segmentation allows each circuit to be optimized for its specific function, reducing the overall processing complexity compared to a unified processing system.
Solution Approach 2:
Focus detection signal processing is extracted from the main imaging signal processing path. By separating the focus detection pixels and their dedicated signal lines, the complex horizontal addition and focus calculation operations are isolated from the main image processing pipeline, reducing overall system complexity.
3Ease of manufacture
If signal lines are arranged in conventional configurations, then manufacturing is simplified, but parasitic capacitance increases and signal processing efficiency decreases
Solution Approach 1:
The signal lines are arranged in a three-dimensional configuration rather than a conventional planar layout. By utilizing vertical stacking and multi-layer routing, the patent reduces parasitic capacitance between adjacent signal lines while maintaining manufacturability through standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration suppresses the lowering of reading speed and simplifies signal processing by enabling efficient analog or digital horizontal addition of pixel signals, improving processing speed and reducing color mixture and cross-talk.
Implementation Method 1
each of which includes a photoelectric conversion portion
Data Source
AI summary
A photoelectric conversion device has a pixel array on which a first pixel to a third pixel are arranged, wherein the first pixel and the second pixel are arranged to be parallel to a first direction, wherein the first pixel is located at a position separated from the second pixel in a positive direction of the first direction, wherein the first pixel is connected to a first signal processing circuit via a first signal line, wherein the second pixel is connected to a second signal processing circuit via a second signal line, wherein the first signal processing circuit and the second signal processing circuit are arranged to be parallel to the first direction, and wherein the first signal processing circuit is located at a position separated from the second signal processing circuit in a direction having a component of a negative direction of the first direction.