Pixel Driving Unit Layout With Overlapping Lines for High-Resolution Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
It is difficult to reduce the width of emissive pixel driving units in display devices, limiting high-resolution capability.
Innovation Solution
The display device is designed with emissive pixel driving units arranged in parallel directions, overlapping gate initialization voltage lines, and auxiliary lines to minimize area consumption and reduce signal coupling defects, allowing for high resolution while maintaining transistor functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the width of emissive pixel driving units is reduced to achieve high resolution, then the resolution capability is improved, but the transistor functionality and signal integrity deteriorate
Solution Approach 1:
The patent applies dimensionality change by arranging circuit elements in three-dimensional space rather than purely two-dimensional layout. Specifically, gate initialization voltage lines are positioned to overlap with boundaries between adjacent emissive pixel driving units, and auxiliary lines are strategically placed to overlap with each other and with gate initialization lines. This vertical stacking and overlapping arrangement in multiple layers allows the circuit to maintain full functionality within a reduced planar footprint, thereby achieving high resolution without sacrificing transistor performance or signal integrity.
Solution Approach 2:
The patent merges multiple circuit functions into shared spatial regions. Gate initialization voltage lines serve as boundaries between adjacent pixel driving units while simultaneously providing initialization functionality. Auxiliary lines are designed to overlap with each other and with gate initialization lines, combining multiple signal paths and control functions into overlapping spatial zones. This merging approach reduces the total area required for circuit elements while maintaining all necessary electrical connections and control functions.
2Area of stationary object
If the width of emissive pixel driving units is reduced, then the area consumption is decreased, but the signal coupling defects increase
Solution Approach 1:
The patent introduces gate initialization voltage lines and auxiliary lines as intermediary elements that mediate between adjacent emissive pixel driving units. These intermediary lines are strategically positioned at boundaries and overlap regions to provide electrical isolation and control signals that prevent unwanted coupling between neighboring pixels. By using these intermediary control lines, the design achieves compact area consumption while actively managing and minimizing signal coupling defects through controlled electrical interactions.
3Manufacturing precision
If the emissive pixel driving units are arranged in parallel directions with overlapping lines, then the high resolution is achieved, but the device complexity increases
Solution Approach 1:
The patent applies universality by designing gate initialization voltage lines and auxiliary lines to perform multiple functions simultaneously. The gate initialization lines serve as both initialization signal carriers and spatial boundaries between adjacent pixel driving units. The auxiliary lines provide both signal routing and overlapping coverage to prevent coupling defects. This multi-functionality reduces the need for separate dedicated elements for each function, thereby achieving high resolution through efficient space utilization without proportionally increasing device complexity.
Data Source
AI summary
A display device includes a substrate, a circuit layer and an element layer, where the circuit layer includes emissive pixel driving units, data lines, first auxiliary lines, second auxiliary lines, and gate initialization voltage lines. The emissive pixel driving units include a first emissive pixel driving unit and a second emissive pixel driving unit, which are disposed adjacent to each other in the second direction. A first gate initialization voltage line among the gate initialization voltage lines which overlaps with a boundary between the first and second emissive pixel driving units. At least a portion of the first emissive pixel driving unit is symmetrical with at least a portion of the second emissive pixel driving unit based on the boundary between the first and second emissive pixel driving units. A portion of at least one of the first auxiliary lines overlaps with the first gate initialization voltage line.