Pixel Circuit Layout to Reduce Sub-Scan Line Parasitic Capacitance
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Solution Overview
Problem
Existing display devices face challenges in achieving excellent image quality due to parasitic capacitance between connecting lines and sub-scan lines, which affect the performance and efficiency of the display.
Innovation Solution
The display device is designed with connection lines that bypass the sub-scan line to avoid overlapping, reducing parasitic capacitance, and includes a specific layout of storage capacitors and transistors to enhance image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If connection lines overlap the sub-scan line to simplify routing, then device complexity is reduced, but parasitic capacitance increases deteriorating image quality
Solution Approach 1:
The connection lines are routed in the first direction (horizontal) while the sub-scan line extends in the second direction (vertical), utilizing orthogonal dimensions to avoid overlap. This dimensional separation eliminates parasitic capacitance between connection lines and sub-scan line while maintaining routing simplicity.
Solution Approach 2:
The pixel circuit is divided into multiple independent pixel circuits (first, second, third pixel circuits) with their respective connection lines routed separately in the first direction. This segmentation allows each connection line to be optimally routed without overlapping the vertically extending sub-scan line, reducing overall parasitic capacitance in the display device.
2Object-affected harmful factors
If storage capacitors are arranged in a specific layout to reduce parasitic capacitance, then image quality is improved, but device area increases
Solution Approach 1:
Storage capacitors are positioned at different locations along the sub-scan line (first storage capacitor at first location, second storage capacitor at second location, third storage capacitor at third location). This spatial distribution in the second direction (vertical) separates the storage capacitors from the connection lines in the first direction (horizontal), reducing parasitic capacitance while efficiently utilizing the pixel circuit area.
3Object-affected harmful factors
If connection lines are routed to bypass the sub-scan line, then parasitic capacitance is reduced improving image quality, but routing complexity increases
Solution Approach 1:
Connection lines are routed in the first direction (horizontal) to connect light emitting parts to pixel circuits, while the sub-scan line extends in the second direction (vertical). This orthogonal routing approach naturally bypasses the sub-scan line without requiring complex detours, reducing parasitic capacitance while maintaining simple routing.
Data Source
AI summary
A display device includes pixels, each of the pixels including light emitting parts disposed in a first direction; pixel circuits including storage capacitors disposed in a second direction intersecting the first direction; a scan line extending in the first direction between the storage capacitors; a sub-scan line electrically connected to the scan line and extending in the second direction; and connection lines that electrically connect the light emitting parts and the pixel circuits and do not overlap the sub-scan line in a plan view.