Electro-Optical Pixel Layout for High Opening Ratio Retention
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Solution Overview
Problem
Existing electro-optical devices face challenges in maintaining a high opening ratio while ensuring the retention capacitor is secure, which affects display quality.
Innovation Solution
The electro-optical device incorporates a scanning line and data line configuration with a transistor having a semiconductor layer that includes source drain regions overlapping the lines, and capacitance elements disposed to overlap the data line, with the capacitance elements configured to include parts of the semiconductor layer, enhancing the retention capacitor without increasing the opening ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the opening ratio is increased, then the display quality is improved, but the retention capacitor is reduced
Solution Approach 1:
The patent merges the transistor and retention capacitor into a single integrated structure where they share common elements (gate electrode, semiconductor layer, insulating layers). This integration allows the retention capacitor to be formed using the same material layers as the transistor, increasing the capacitor area without requiring additional material deposition steps, thereby maintaining high opening ratio while securing sufficient retention capacitor.
Solution Approach 2:
The patent utilizes the vertical stacking dimension to form the retention capacitor. By forming the capacitor using stacked insulating layers and conductive layers in the vertical direction above the substrate, the design achieves increased capacitor area without expanding the planar footprint, thus maintaining high opening ratio while providing adequate retention capacitance.
2Illumination intensity
If the opening ratio is increased, then the light transmission is improved, but the area for retention capacitor is reduced
Solution Approach 1:
The retention capacitor is formed by stacking insulating and conductive layers in the vertical dimension above the substrate. This vertical stacking approach increases the effective capacitor area without consuming additional planar space, allowing high opening ratio for light transmission while providing sufficient area for the retention capacitor.
Solution Approach 2:
The gate electrode and semiconductor layer of the transistor serve dual functions: as switching elements and as electrode/structural components for the retention capacitor. This multi-functionality allows the same material layers to contribute to both transistor operation and capacitor formation, maximizing the use of available space for light transmission.
Data Source
AI summary
Provided are a scanning line extending along a first direction, a data line extending along a second direction intersecting the first direction, a TFT having a semiconductor layer including one source drain region and a channel region extending along the first direction, at a position overlapping the scanning line in plan view, and another source drain region extending along the second direction, at a position overlapping the data line in plan view, and a first capacitance element and a second capacitance element disposed at a position overlapping the data line, and the first capacitance element and the second capacitance element are configured to include a part of the semiconductor layer.