Symmetrical Pixel Circuit Layout for Faster Display Signal Routing
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Solution Overview
Problem
Existing display devices experience signal delays due to inefficient data signal transmission paths, leading to reduced display quality and performance.
Innovation Solution
The display device incorporates symmetrical pixel circuits and connection lines between adjacent pixel rows, sharing horizontal power lines and utilizing multiple connection lines to shorten signal transmission paths, thereby optimizing data signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data lines extend directly across the display panel without connection lines, then the structure is simple, but signal delay increases due to long transmission paths
Solution Approach 1:
The patent segments the data transmission path by introducing connection lines between adjacent pixel rows. These connection lines divide the long transmission path into shorter segments, allowing data signals to travel shorter distances and reducing overall signal delay while maintaining a manageable structural complexity.
Solution Approach 2:
The patent introduces connection lines that extend in the first direction (horizontal) between pixel rows arranged in the second direction (vertical). This adds a dimensional component to the data transmission path, creating a two-dimensional routing network that shortens the effective transmission distance compared to purely vertical data line extensions.
2Productivity
If pixel circuits are arranged asymmetrically, then layout is easier, but signal transmission efficiency decreases due to unequal path lengths
Solution Approach 1:
The patent employs asymmetric pixel circuit layouts within symmetric pairs. Each pixel circuit is designed with specific transistor arrangements that are asymmetric in themselves, but when paired with adjacent pixel circuits and connected through connection lines, they form symmetric transmission paths. This allows efficient signal transmission while maintaining manufacturing feasibility through standardized asymmetric unit designs.
Solution Approach 2:
The patent applies different transistor configurations and connection arrangements to different regions of the display panel. Specifically, pixel circuits in adjacent rows are designed with localized variations in transistor placement and connection line routing, optimizing signal transmission for each local region while maintaining overall symmetry and manufacturing consistency.
3Loss of time
If multiple connection lines are added between pixel rows, then signal delay is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple connection lines into shared pathways where possible. Adjacent pixel rows share common connection lines and power lines, reducing the total number of unique fabrication steps required. This merging approach allows multiple data transmission paths to coexist while minimizing the overall manufacturing complexity and process steps.
Data Source
AI summary
A display device is disclosed that includes first and second gate lines extending in a first direction and arranged along a second direction. Data lines extend in the second direction and are arranged along the first direction. First pixels are connected to the first gate line in common and the data lines respectively. Second pixels are connected to the second gate line in common and the data lines respectively. Connection lines are disposed between the first and second gate lines, and at least one of the connection lines is connected to a corresponding data line. Each of the first and second pixels includes a light emitting element and a pixel circuit including transistors. The pixel circuit of a first pixel of the first pixels and the pixel circuit of a second pixel of the seconds pixel are symmetrical with respect to a connection line of the connection lines in a plan view.