Pixel Structure Layout for Vertical Crosstalk Reduction
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Solution Overview
Problem
Conventional ultra-high-definition liquid crystal displays with narrow bezels experience display abnormalities due to parasitic capacitances between data lines and pixel units, causing vertical crosstalk and affecting product quality.
Innovation Solution
A pixel structure with a modified data line configuration, comprising first, second, and third data line sections, arranged symmetrically and electrically connected, which reduces resistance and capacitance load, and increases charging rate, thereby offsetting the coupling effect from parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If data lines are positioned close to pixel units to achieve narrow bezel design, then the bezel width is reduced, but parasitic capacitance between data lines and pixel units increases causing vertical crosstalk
Solution Approach 1:
The data line is divided into three sections: first data line section (between main pixel regions), second data line section (on sub-pixel region of first pixel unit), and third data line section (on sub-pixel region of second pixel unit). This segmentation allows different portions of the data line to serve different functions and reduces overall parasitic capacitance impact on pixel units.
Solution Approach 2:
The second and third data line sections are extracted from the conventional single continuous data line path and positioned specifically on sub-pixel regions. This extraction allows the data line to bypass areas that would create excessive parasitic capacitance with pixel unit electrodes, thereby reducing vertical crosstalk while maintaining narrow bezel design.
2Device complexity
If conventional single-section data line configuration is used, then the structure is simple, but resistance and capacitance load are high resulting in low charging rate
Solution Approach 1:
The data line is segmented into three distinct sections with different routing paths. The first data line section connects between main pixel regions, while the second and third sections are positioned on sub-pixel regions of adjacent pixel units. This segmentation reduces the overall resistance and capacitance load by optimizing the current path, thereby increasing the charging rate to the pixel units.
Solution Approach 2:
Different sections of the data line are positioned in different locations with different electrical characteristics. The second and third data line sections are specifically positioned on sub-pixel regions where they experience different parasitic capacitance conditions compared to the first data line section. This local quality variation optimizes the overall electrical performance by reducing total resistance and capacitance load.
Data Source
AI summary
The present application provides a pixel structure and a display panel. The pixel structure includes pixel units, data lines, and scan lines. The pixel unit includes a main pixel region and a sub-pixel region. Each data line includes a first data line section, a second data line section, and a third data line section. Each first data line section is arranged between the two main pixel regions of two adjacent pixel units. The second data line section and the third data line section are arranged in the two sub-pixel regions of adjacent two pixel units, respectively.