Pixel Circuit With Leakage Compensation for Stable Grayscale Luminance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices struggle to stably implement high and low grayscale luminance while minimizing leakage currents, which affects display quality and stability.
Innovation Solution
A pixel design incorporating specific transistor configurations and capacitors to maintain constant leakage current direction and minimize gate electrode voltage changes, ensuring stable operation at varying grayscale levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a pixel is designed to drive at high speed with high frame frequency, then the response time is reduced and productivity is improved, but leakage current increases and luminance stability deteriorates
Solution Approach 1:
The pixel circuit is divided into multiple functional blocks: a driving transistor for current control, a switching transistor for signal input, a storage capacitor for voltage holding, and a compensation circuit for leakage current correction. This segmentation allows each component to optimize its function, with the storage capacitor maintaining gate voltage stability during high-speed operation despite leakage currents.
Solution Approach 2:
The pixel incorporates a compensation circuit that monitors and corrects for leakage current effects on the storage capacitor voltage. By implementing feedback mechanisms, the circuit can maintain accurate grayscale levels and luminance stability even when operating at high frame frequencies where leakage currents become more significant.
2Reliability
If a pixel is designed to drive at low speed with low frame frequency, then leakage current effects are reduced and luminance stability is improved, but productivity decreases
Solution Approach 1:
The storage capacitor is pre-charged to the required gate voltage during the programming phase before the emission period begins. This preliminary action ensures that the gate voltage is established and maintained, preventing luminance instability during the actual display period regardless of the frame frequency, thereby enabling stable operation at both high and low speeds.
3Reliability
If the storage capacitor capacity is increased to maintain gate voltage stability, then luminance consistency is improved, but device complexity and area increase
Solution Approach 1:
The patent optimizes the storage capacitor value to a specific range that provides sufficient voltage holding capability for high-speed operation without excessive size. By carefully selecting capacitance parameters and adjusting other circuit parameters accordingly, the design achieves luminance stability without requiring oversized capacitors that would increase pixel area and complexity.
4Reliability
If the storage capacitor capacity is increased to maintain gate voltage stability, then luminance consistency is improved, but manufacturing cost increases
Solution Approach 1:
The patent determines an optimal storage capacitor value that achieves the required luminance consistency without excessive capacitance. This optimized parameter selection reduces the capacitor area and associated manufacturing complexity, thereby lowering production costs while maintaining sufficient voltage holding performance for high-speed display operation.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
According to embodiments of the disclosure, a pixel includes a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line via a second node, and a second electrode connected to a first electrode of a light emitting element via a third node, a light emitting element configured to output light in response to a driving current supplied from the first transistor and including a second electrode connected to a second power line, a second transistor connected between a data line and the second node and including a gate electrode connected to a first scan line, a third transistor including a first sub-transistor and a second sub-transistor connected in series between the first node and the third node, and a first capacitor connected between a first common node between the first sub-transistor and the second sub-transistor and the first electrode.