Pixel Circuit Leakage Current Reduction via Dual Gate Capacitance
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Solution Overview
Problem
Display devices face challenges in reducing leakage current through transistors, which affects display quality due to limitations in securing sufficient capacitance between transistor nodes and storage lines.
Innovation Solution
The pixel circuit incorporates a dual gate structure with additional hold patterns and storage lines that overlap specific regions, forming multiple capacitors to increase capacitance between intermediate nodes and storage lines, thereby reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual gate structure is used to reduce leakage current, then display quality is improved, but device complexity increases
Solution Approach 1:
The transistor gate is divided into two separate gates (first gate electrode and second gate electrode) that can be independently controlled. This segmentation allows independent optimization of each gate's function - one gate controls the main current flow while the other suppresses leakage current, thereby improving display quality without requiring a completely new transistor design
2Reliability
If capacitance between transistor nodes and storage lines is increased to reduce leakage current, then display quality is improved, but area occupied increases
Solution Approach 1:
The storage line is positioned to overlap with the intermediate node in the vertical dimension (different layers), creating capacitance through spatial overlap rather than lateral expansion. This allows sufficient capacitance to be achieved without increasing the planar area of the pixel circuit, maintaining high resolution while reducing leakage current
3Reliability
If hold patterns and storage lines are added to form multiple capacitors, then leakage current is reduced, but manufacturing complexity increases
Solution Approach 1:
The hold pattern is integrated with the existing storage line structure, and both are formed using the same conductive material layer. This merging approach allows multiple capacitor functions to be achieved without adding separate manufacturing steps, as the hold pattern and storage line are deposited together in a single fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances display quality by minimizing leakage current, preventing flicker at low frequencies and improving overall display performance.
Implementation Method 1
a first hold pattern which overlaps the first sub-drain region, the second sub-source region, and the storage line in a plan view, and connected to the first sub-drain region and the second sub-source region
Data Source
AI summary
A pixel may include a light emitting diode which includes an anode and a cathode, a first transistor which includes a first source region, a first drain region electrically connected to the anode, a first channel region, and a first gate electrode, a first sub-transistor which includes a first sub-source region connected to the first drain region, a first sub-drain region, a first sub-channel region, and a first sub-gate electrode, a second sub-transistor which includes a second sub-source region connected to the first sub-drain region, a second sub-drain region connected to the first gate electrode, a second sub-channel region, and a second sub-gate electrode, a storage line which overlaps the first sub-drain region and the second sub-source region, and a first hold pattern which overlaps the first sub-drain region, the second sub-source region, and the storage line, and connected to the first sub-drain region and the second sub-source region.